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[Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-04 03:41:21 +00:00
parent 6c46ca33bf
commit 152ac18e80
4 changed files with 27 additions and 3 deletions
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5
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
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@ -8,6 +8,7 @@
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/HexagonBaseInfo.h"
#include "MCTargetDesc/HexagonMCInst.h"
#include "MCTargetDesc/HexagonMCTargetDesc.h"
#include "llvm/MC/MCContext.h"
@ -110,5 +111,7 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
// Remove parse bits.
insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK);
return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
DecodeStatus Result = decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
HexagonMCInst::AppendImplicitOperands(MI);
return Result;
}

2
lib/Target/Hexagon/Disassembler/LLVMBuild.txt
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@ -19,5 +19,5 @@
type = Library
name = HexagonDisassembler
parent = Hexagon
required_libraries = HexagonInfo MCDisassembler Support
required_libraries = HexagonDesc HexagonInfo MCDisassembler Support
add_to_library_groups = Hexagon

5
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -170,12 +170,13 @@ multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
}
let isCodeGenOnly = 0 in
let isCodeGenOnly = 0 in {
defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
}
// Pats for instruction selection.
class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
@ -275,11 +276,13 @@ multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
}
}
let isCodeGenOnly = 0 in {
defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
}
// Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
// Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has

18
test/MC/Disassembler/Hexagon/alu32_alu.txt Normal file
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@ -0,0 +1,18 @@
# XFAIL: arm-windows
# XFAIL: arm-linux
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
0x11 0xdf 0x15 0xf3
# CHECK: r17 = add(r21, r31)
0x11 0xdf 0x15 0xf1
# CHECK: r17 = and(r21, r31)
0x11 0xdf 0x35 0xf1
# CHECK: r17 = or(r21, r31)
0x11 0xdf 0x75 0xf1
# CHECK: r17 = xor(r21, r31)
0x11 0xdf 0x35 0xf3
# CHECK: r17 = sub(r31, r21)
0x11 0xc0 0xbf 0x70
# CHECK: r17 = sxtb(r31)
0x11 0xc0 0xd5 0x70
# CHECK: r17 = zxth(r21)