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lower PPC::MFCRpseud when transforming to MC, avoiding calling

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the aborting printSpecial() method.  This gets us to 8 failures.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119084 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-11-14 22:03:15 +00:00
parent 959fb3dd5c
commit 2ead458ae8
2 changed files with 18 additions and 2 deletions
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13
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -554,13 +554,22 @@ void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
///
void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
if (UseInstPrinter) {
MCInst TmpInst;
// Lower multi-instruction pseudo operations.
switch (MI->getOpcode()) {
default: break;
// TODO: implement me.
case PPC::MFCRpseud:
// Transform: %R3 = MFCRpseud %CR7
// Into: %R3 = MFCR ;; cr7
OutStreamer.AddComment(getRegisterName(MI->getOperand(1).getReg()));
TmpInst.setOpcode(PPC::MFCR);
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
OutStreamer.EmitInstruction(TmpInst);
return;
}
MCInst TmpInst;
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
OutStreamer.EmitInstruction(TmpInst);
return;

7
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -1120,9 +1120,16 @@ def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
// As it turns out, in all cases where we currently use this,
// we're only interested in one subregister of it. Represent this in the
// instruction to keep the register allocator from becoming confused.
//
// FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
"mfcr $rT ${:comment} $FXM", SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU;
def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
"mfcr $rT", SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU;
def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
"mfcr $rT, $FXM", SprMFCR>,
PPC970_DGroup_First, PPC970_Unit_CRU;