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Fix typo in comment. Take out some random whitespace.

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(Partial merge from my working file)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8564 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2003-09-16 15:38:05 +00:00
parent e655a637a7
commit 305f02dd64
2 changed files with 2 additions and 8 deletions
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5
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
View File

@ -1397,18 +1397,16 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// The entry pont to Register Allocation // The entry point to Register Allocation
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
void PhyRegAlloc::allocateRegisters() void PhyRegAlloc::allocateRegisters()
{ {
// make sure that we put all register classes into the RegClassList // make sure that we put all register classes into the RegClassList
// before we call constructLiveRanges (now done in the constructor of // before we call constructLiveRanges (now done in the constructor of
// PhyRegAlloc class). // PhyRegAlloc class).
// //
LRI.constructLiveRanges(); // create LR info LRI.constructLiveRanges(); // create LR info
if (DEBUG_RA >= RA_DEBUG_LiveRanges) if (DEBUG_RA >= RA_DEBUG_LiveRanges)
LRI.printLiveRanges(); LRI.printLiveRanges();
@ -1416,7 +1414,6 @@ void PhyRegAlloc::allocateRegisters()
buildInterferenceGraphs(); // build IGs in all reg classes buildInterferenceGraphs(); // build IGs in all reg classes
if (DEBUG_RA >= RA_DEBUG_LiveRanges) { if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
// print all LRs in all reg classes // print all LRs in all reg classes
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++) for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)

5
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
View File

@ -1397,18 +1397,16 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// The entry pont to Register Allocation // The entry point to Register Allocation
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
void PhyRegAlloc::allocateRegisters() void PhyRegAlloc::allocateRegisters()
{ {
// make sure that we put all register classes into the RegClassList // make sure that we put all register classes into the RegClassList
// before we call constructLiveRanges (now done in the constructor of // before we call constructLiveRanges (now done in the constructor of
// PhyRegAlloc class). // PhyRegAlloc class).
// //
LRI.constructLiveRanges(); // create LR info LRI.constructLiveRanges(); // create LR info
if (DEBUG_RA >= RA_DEBUG_LiveRanges) if (DEBUG_RA >= RA_DEBUG_LiveRanges)
LRI.printLiveRanges(); LRI.printLiveRanges();
@ -1416,7 +1414,6 @@ void PhyRegAlloc::allocateRegisters()
buildInterferenceGraphs(); // build IGs in all reg classes buildInterferenceGraphs(); // build IGs in all reg classes
if (DEBUG_RA >= RA_DEBUG_LiveRanges) { if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
// print all LRs in all reg classes // print all LRs in all reg classes
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++) for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)