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[DAGCombiner] Show missed opportunity to UNDEF out-of-range SHL

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Fails to match constant shift value due to presence of AND mask.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286452 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim 2016-11-10 14:19:45 +00:00
parent 541a4fd75d
commit 3cc160451c
1 changed files with 15 additions and 0 deletions
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15
test/CodeGen/X86/combine-shl.ll
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@ -44,6 +44,21 @@ define <4 x i32> @combine_vec_shl_outofrange1(<4 x i32> %x) {
ret <4 x i32> %1
}
define <4 x i32> @combine_vec_shl_outofrange2(<4 x i32> %a0) {
; SSE-LABEL: combine_vec_shl_outofrange2:
; SSE: # BB#0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_shl_outofrange2:
; AVX: # BB#0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = and <4 x i32> %a0, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
%2 = shl <4 x i32> %1, <i32 33, i32 33, i32 33, i32 33>
ret <4 x i32> %2
}
; fold (shl x, 0) -> x
define <4 x i32> @combine_vec_shl_by_zero(<4 x i32> %x) {
; SSE-LABEL: combine_vec_shl_by_zero: