RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-25 20:59:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

R600: Rename 128 bit registers.

Browse Source 
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182124 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2013-05-17 16:50:09 +00:00
parent 25c209e9a2
commit 4109bd8829
3 changed files with 25 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/R600/R600Instructions.td
View File

@ -1751,8 +1751,7 @@ let usesCustomInserter = 1 in {
class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
list<dag> pattern>
: EG_CF_RAT <0x57, 0x2, 0, (outs), ins,
!strconcat(name, " $rw_gpr, $index_gpr, $eop"), pattern> {
: EG_CF_RAT <0x57, 0x2, 0, (outs), ins, name, pattern> {
let RIM = 0;
// XXX: Have a separate instruction for non-indexed writes.
let TYPE = 1;
@ -1772,19 +1771,19 @@ class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
// 32-bit store
def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
(ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
0x1, "RAT_WRITE_CACHELESS_32_eg",
0x1, "RAT_WRITE_CACHELESS_32_eg $rw_gpr, $index_gpr, $eop",
[(global_store i32:$rw_gpr, i32:$index_gpr)]
>;
//128-bit store
def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
(ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
0xf, "RAT_WRITE_CACHELESS_128",
0xf, "RAT_WRITE_CACHELESS_128 $rw_gpr.XYZW, $index_gpr, $eop",
[(global_store v4i32:$rw_gpr, i32:$index_gpr)]
>;
class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
: InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern>,
: InstR600ISA <outs, (ins MEMxi:$ptr), name, pattern>,
VTX_WORD1_GPR, VTX_WORD0 {
// Static fields
@ -1839,7 +1838,7 @@ class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
}
class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_eg <"VTX_READ_8", buffer_id, (outs R600_TReg32_X:$dst),
: VTX_READ_eg <"VTX_READ_8 $dst, $ptr", buffer_id, (outs R600_TReg32_X:$dst),
pattern> {
let MEGA_FETCH_COUNT = 1;
@ -1851,7 +1850,7 @@ class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
}
class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_eg <"VTX_READ_16", buffer_id, (outs R600_TReg32_X:$dst),
: VTX_READ_eg <"VTX_READ_16 $dst, $ptr", buffer_id, (outs R600_TReg32_X:$dst),
pattern> {
let MEGA_FETCH_COUNT = 2;
let DST_SEL_X = 0;
@ -1863,7 +1862,7 @@ class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
}
class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_eg <"VTX_READ_32", buffer_id, (outs R600_TReg32_X:$dst),
: VTX_READ_eg <"VTX_READ_32 $dst, $ptr", buffer_id, (outs R600_TReg32_X:$dst),
pattern> {
let MEGA_FETCH_COUNT = 4;
@ -1884,7 +1883,7 @@ class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
}
class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
: VTX_READ_eg <"VTX_READ_128 $dst.XYZW, $ptr", buffer_id, (outs R600_Reg128:$dst),
pattern> {
let MEGA_FETCH_COUNT = 16;

2
lib/Target/R600/R600RegisterInfo.td
View File

@ -35,7 +35,7 @@ foreach Index = 0-127 in {
Chan>;
}
// 128-bit Temporary Registers
def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW",
def T#Index#_XYZW : R600Reg_128 <"T"#Index#"",
[!cast<Register>("T"#Index#"_X"),
!cast<Register>("T"#Index#"_Y"),
!cast<Register>("T"#Index#"_Z"),

32
test/CodeGen/R600/llvm.AMDGPU.tex.ll
View File

@ -1,21 +1,21 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 1
;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 2
;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 3
;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 4
;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 5
;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 6
;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 7
;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 8
;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 9
;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 10
;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 11
;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 12
;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 13
;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 14
;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 15
;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 16
;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 1
;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 2
;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 3
;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 4
;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 5
;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 6
;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 7
;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 8
;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 9
;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 10
;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 11
;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 12
;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 13
;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 14
;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 15
;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 16
define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
%addr = load <4 x float> addrspace(1)* %in