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Kill the x86 pattern isel. boom.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26246 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2006-02-17 00:03:04 +00:00
parent dc8acb6420
commit 4c5dcf54ff
4 changed files with 215 additions and 3977 deletions
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8
lib/Target/X86/X86.h
View File

@ -25,14 +25,6 @@ class FunctionPass;
class IntrinsicLowering;
class MachineCodeEmitter;
extern bool X86PatIsel;
/// createX86ISelPattern - This pass converts an LLVM function into a
/// machine code representation using pattern matching and a machine
/// description file.
///
FunctionPass *createX86ISelPattern(TargetMachine &TM);
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///

97
lib/Target/X86/X86ISelLowering.cpp
View File

@ -70,13 +70,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
// this operation.
setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
if (X86ScalarSSE)
// SSE has no i16 to fp conversion, only i32
if (X86ScalarSSE)
setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
else if (!X86PatIsel) {
setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
}
// We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64
// isn't legal.
@ -112,9 +108,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
if (!X86PatIsel) {
setOperationAction(ISD::BRCOND , MVT::Other, Custom);
}
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::BR_CC , MVT::Other, Expand);
@ -136,16 +130,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
if (X86PatIsel) {
setOperationAction(ISD::BSWAP , MVT::i32 , Expand);
setOperationAction(ISD::ROTL , MVT::i8 , Expand);
setOperationAction(ISD::ROTR , MVT::i8 , Expand);
setOperationAction(ISD::ROTL , MVT::i16 , Expand);
setOperationAction(ISD::ROTR , MVT::i16 , Expand);
setOperationAction(ISD::ROTL , MVT::i32 , Expand);
setOperationAction(ISD::ROTR , MVT::i32 , Expand);
}
setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
setOperationAction(ISD::READIO , MVT::i1 , Expand);
@ -160,7 +144,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
// These should be promoted to a larger select which is supported.
setOperationAction(ISD::SELECT , MVT::i1 , Promote);
setOperationAction(ISD::SELECT , MVT::i8 , Promote);
if (!X86PatIsel) {
// X86 wants to expand cmov itself.
setOperationAction(ISD::SELECT , MVT::i16 , Custom);
setOperationAction(ISD::SELECT , MVT::i32 , Custom);
@ -184,7 +168,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
// X86 wants to expand memset / memcpy itself.
setOperationAction(ISD::MEMSET , MVT::Other, Custom);
setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
}
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
@ -473,7 +456,6 @@ X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
break;
}
if (!X86PatIsel) {
std::vector<MVT::ValueType> NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
@ -566,41 +548,6 @@ X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
}
return std::make_pair(RetVal, Chain);
} else {
std::vector<SDOperand> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
Ops.push_back(DAG.getConstant(0, getPointerTy()));
SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL :X86ISD::CALL,
RetVals, Ops);
SDOperand ResultVal;
switch (RetTyVT) {
case MVT::isVoid: break;
default:
ResultVal = TheCall.getValue(1);
break;
case MVT::i1:
case MVT::i8:
case MVT::i16:
ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
break;
case MVT::f32:
// FIXME: we would really like to remember that this FP_ROUND operation is
// okay to eliminate if we allow excess FP precision.
ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
break;
case MVT::i64:
ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
TheCall.getValue(2));
break;
}
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
return std::make_pair(ResultVal, Chain);
}
}
//===----------------------------------------------------------------------===//
@ -947,7 +894,6 @@ X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
break;
}
if (!X86PatIsel) {
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into registers.
SDOperand InFlag;
@ -1065,45 +1011,6 @@ X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
}
return std::make_pair(RetVal, Chain);
} else {
std::vector<SDOperand> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
// Callee pops all arg values on the stack.
Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
// Pass register arguments as needed.
Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL :X86ISD::CALL,
RetVals, Ops);
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
SDOperand ResultVal;
switch (RetTyVT) {
case MVT::isVoid: break;
default:
ResultVal = TheCall.getValue(1);
break;
case MVT::i1:
case MVT::i8:
case MVT::i16:
ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
break;
case MVT::f32:
// FIXME: we would really like to remember that this FP_ROUND operation is
// okay to eliminate if we allow excess FP precision.
ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
break;
case MVT::i64:
ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
TheCall.getValue(2));
break;
}
return std::make_pair(ResultVal, Chain);
}
}
SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {

3648
lib/Target/X86/X86ISelPattern.cpp
View File

File diff suppressed because it is too large Load Diff

13
lib/Target/X86/X86TargetMachine.cpp
View File

@ -26,8 +26,6 @@
#include <iostream>
using namespace llvm;
bool llvm::X86PatIsel = true;
/// X86TargetMachineModule - Note that this is used on hosts that cannot link
/// in a library unless there are references into the library. In particular,
/// it seems that it is not possible to get things to work on Win32 without
@ -39,11 +37,6 @@ namespace {
cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
cl::desc("Disable the X86 asm printer, for use "
"when profiling the code generator."));
cl::opt<bool, true> EnableX86PatISel("enable-x86-pattern-isel", cl::Hidden,
cl::desc("Enable the pattern based isel for X86"),
cl::location(X86PatIsel),
cl::init(false));
// Register the target.
RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
}
@ -107,9 +100,6 @@ bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
PM.add(createUnreachableBlockEliminationPass());
// Install an instruction selector.
if (X86PatIsel)
PM.add(createX86ISelPattern(*this));
else
PM.add(createX86ISelDag(*this));
// Print the instruction selected machine code...
@ -172,9 +162,6 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
PM.add(createUnreachableBlockEliminationPass());
// Install an instruction selector.
if (X86PatIsel)
PM.add(createX86ISelPattern(TM));
else
PM.add(createX86ISelDag(TM));
// Print the instruction selected machine code...