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[AMDGPU] Some code cleaning in SIRegisterInfo.td

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Reviewers: tstellarAMD, vpykhtin

Subscribers: arsenm, kzhuravl

Differential Revision: https://reviews.llvm.org/D22620

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276274 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sam Kolton 2016-07-21 13:29:57 +00:00
parent a264c851a4
commit 50e9ffb710
1 changed files with 23 additions and 33 deletions
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56
lib/Target/AMDGPU/SIRegisterInfo.td
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@ -248,11 +248,6 @@ def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
// Register classes used as source and destination
//===----------------------------------------------------------------------===//
class RegImmMatcher<string name> : AsmOperandClass {
let Name = name;
let RenderMethod = "addRegOrImmOperands";
}
// Subset of SReg_32 without M0 for SMRD instructions and alike.
// See comments in SIInstructions.td for more info.
def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32], 32,
@ -344,6 +339,16 @@ def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
let Size = 32;
}
def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>;
def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> {
let CopyCost = 2;
}
//===----------------------------------------------------------------------===//
// Register operands
//===----------------------------------------------------------------------===//
class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
let OperandNamespace = "AMDGPU";
let OperandType = "OPERAND_REG_IMM32";
@ -354,6 +359,11 @@ class RegInlineOperand <RegisterClass rc> : RegisterOperand<rc> {
let OperandType = "OPERAND_REG_INLINE_C";
}
class RegImmMatcher<string name> : AsmOperandClass {
let Name = name;
let RenderMethod = "addRegOrImmOperands";
}
//===----------------------------------------------------------------------===//
// SSrc_* Operands with an SGPR or a 32-bit immediate
//===----------------------------------------------------------------------===//
@ -374,25 +384,19 @@ def SCSrc_32 : RegInlineOperand<SReg_32> {
let ParserMatchClass = RegImmMatcher<"SCSrc32">;
}
def SCSrc_64 : RegInlineOperand<SReg_64> {
let ParserMatchClass = RegImmMatcher<"SCSrc64">;
}
//===----------------------------------------------------------------------===//
// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
//===----------------------------------------------------------------------===//
def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>;
def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> {
let CopyCost = 2;
}
def VSrc_32 : RegisterOperand<VS_32> {
let OperandNamespace = "AMDGPU";
let OperandType = "OPERAND_REG_IMM32";
def VSrc_32 : RegImmOperand<VS_32> {
let ParserMatchClass = RegImmMatcher<"VSrc32">;
}
def VSrc_64 : RegisterOperand<VS_64> {
let OperandNamespace = "AMDGPU";
let OperandType = "OPERAND_REG_IMM32";
def VSrc_64 : RegImmOperand<VS_64> {
let ParserMatchClass = RegImmMatcher<"VSrc64">;
}
@ -411,24 +415,10 @@ def VRegSrc_32 : RegisterOperand<VGPR_32> {
// VCSrc_* Operands with an SGPR, VGPR or an inline constant
//===----------------------------------------------------------------------===//
def VCSrc_32 : RegisterOperand<VS_32> {
let OperandNamespace = "AMDGPU";
let OperandType = "OPERAND_REG_INLINE_C";
def VCSrc_32 : RegInlineOperand<VS_32> {
let ParserMatchClass = RegImmMatcher<"VCSrc32">;
}
def VCSrc_64 : RegisterOperand<VS_64> {
let OperandNamespace = "AMDGPU";
let OperandType = "OPERAND_REG_INLINE_C";
def VCSrc_64 : RegInlineOperand<VS_64> {
let ParserMatchClass = RegImmMatcher<"VCSrc64">;
}
//===----------------------------------------------------------------------===//
// SCSrc_* Operands with an SGPR or an inline constant
//===----------------------------------------------------------------------===//
def SCSrc_64 : RegisterOperand<SReg_64> {
let OperandNamespace = "AMDGPU";
let OperandType = "OPERAND_REG_INLINE_C";
let ParserMatchClass = RegImmMatcher<"SCSrc64">;
}