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Implement a TODO: for any shuffle that can be viewed as a v4[if]32 shuffle,
if it can be implemented in 3 or fewer discrete altivec instructions, codegen it as such. This implements Regression/CodeGen/PowerPC/vec_perf_shuffle.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27748 91177308-0d34-0410-b5e6-96231b3b80d8
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Chris Lattner
parent
c3b5ad944c
commit
5913810b82
@ -13,6 +13,7 @@
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#include "PPCISelLowering.h"
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#include "PPCTargetMachine.h"
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#include "PPCPerfectShuffle.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/Analysis/ScalarEvolutionExpressions.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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@ -1123,6 +1124,88 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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return SDOperand();
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}
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/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
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/// the specified operations to build the shuffle.
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static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
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SDOperand RHS, SelectionDAG &DAG) {
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unsigned OpNum = (PFEntry >> 26) & 0x0F;
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unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
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unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
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enum {
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OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
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OP_VMRGHW,
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OP_VMRGLW,
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OP_VSPLTISW0,
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OP_VSPLTISW1,
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OP_VSPLTISW2,
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OP_VSPLTISW3,
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OP_VSLDOI4,
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OP_VSLDOI8,
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OP_VSLDOI12,
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};
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if (OpNum == OP_COPY) {
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if (LHSID == (1*9+2)*9+3) return LHS;
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assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
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return RHS;
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}
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unsigned ShufIdxs[16];
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switch (OpNum) {
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default: assert(0 && "Unknown i32 permute!");
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case OP_VMRGHW:
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ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
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ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
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ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
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ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
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break;
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case OP_VMRGLW:
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ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
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ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
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ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
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ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
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break;
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case OP_VSPLTISW0:
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for (unsigned i = 0; i != 16; ++i)
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ShufIdxs[i] = (i&3)+0;
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break;
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case OP_VSPLTISW1:
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for (unsigned i = 0; i != 16; ++i)
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ShufIdxs[i] = (i&3)+4;
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break;
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case OP_VSPLTISW2:
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for (unsigned i = 0; i != 16; ++i)
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ShufIdxs[i] = (i&3)+8;
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break;
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case OP_VSPLTISW3:
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for (unsigned i = 0; i != 16; ++i)
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ShufIdxs[i] = (i&3)+12;
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break;
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case OP_VSLDOI4:
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for (unsigned i = 0; i != 16; ++i)
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ShufIdxs[i] = i+4;
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break;
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case OP_VSLDOI8:
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for (unsigned i = 0; i != 16; ++i)
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ShufIdxs[i] = i+8;
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break;
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case OP_VSLDOI12:
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for (unsigned i = 0; i != 16; ++i)
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ShufIdxs[i] = i+12;
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break;
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}
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std::vector<SDOperand> Ops;
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for (unsigned i = 0; i != 16; ++i)
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Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
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SDOperand OpLHS, OpRHS;
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OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
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OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
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DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
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}
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/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
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/// is a shuffle we can handle in a single instruction, return it. Otherwise,
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/// return the code it can be lowered into. Worst case, it can always be
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@ -1166,8 +1249,58 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
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return Op;
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// TODO: Handle more cases, and also handle cases that are cheaper to do as
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// multiple such instructions than as a constant pool load/vperm pair.
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// Check to see if this is a shuffle of 4-byte values. If so, we can use our
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// perfect shuffle table to emit an optimal matching sequence.
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unsigned PFIndexes[4];
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bool isFourElementShuffle = true;
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for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
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unsigned EltNo = 8; // Start out undef.
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for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
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if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
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continue; // Undef, ignore it.
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unsigned ByteSource =
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cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
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if ((ByteSource & 3) != j) {
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isFourElementShuffle = false;
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break;
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}
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if (EltNo == 8) {
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EltNo = ByteSource/4;
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} else if (EltNo != ByteSource/4) {
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isFourElementShuffle = false;
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break;
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}
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}
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PFIndexes[i] = EltNo;
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}
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// If this shuffle can be expressed as a shuffle of 4-byte elements, use the
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// perfect shuffle vector to determine if it is cost effective to do this as
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// discrete instructions, or whether we should use a vperm.
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if (isFourElementShuffle) {
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// Compute the index in the perfect shuffle table.
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unsigned PFTableIndex =
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PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
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unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
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unsigned Cost = (PFEntry >> 30);
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// Determining when to avoid vperm is tricky. Many things affect the cost
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// of vperm, particularly how many times the perm mask needs to be computed.
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// For example, if the perm mask can be hoisted out of a loop or is already
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// used (perhaps because there are multiple permutes with the same shuffle
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// mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
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// the loop requires an extra register.
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//
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// As a compromise, we only emit discrete instructions if the shuffle can be
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// generated in 3 or fewer operations. When we have loop information
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// available, if this block is within a loop, we should avoid using vperm
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// for 3-operation perms and use a constant pool load instead.
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if (Cost < 3)
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return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
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}
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// Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
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// vector that will get spilled to the constant pool.
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@ -101,18 +101,6 @@ void test(vector int *X, vector int *Y) {
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//===----------------------------------------------------------------------===//
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There are a wide variety of vector_shuffle operations that we can do with a pair
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of instructions (e.g. a vsldoi + vpkuhum). We should pattern match these, but
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there are a huge number of these.
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Specific examples:
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C = vector_shuffle A, B, <0, 1, 2, 4>
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-> t = vsldoi A, A, 12
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-> C = vsldoi A, B, 4
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//===----------------------------------------------------------------------===//
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extract_vector_elt of an arbitrary constant vector can be done with the
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following instructions:
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