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Cleanup the scalar FMA3 definitions. Add patterns to fold loads with scalar forms.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162260 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-08-21 07:11:11 +00:00
parent e4b6189658
commit 5f67d94697
1 changed files with 49 additions and 44 deletions
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93
lib/Target/X86/X86InstrFMA.td
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@ -245,23 +245,27 @@ let Predicates = [HasFMA] in {
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst" in {
multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
RegisterClass RC> { RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
let neverHasSideEffects = 1 in { SDPatternOperator OpNode = null_frag, bit MayLoad = 1> {
def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3), (ins RC:$src1, RC:$src2, RC:$src3),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>; "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
let mayLoad = 1 in [(set RC:$dst,
def m : FMA3<opc, MRMSrcMem, (outs RC:$dst), (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
(ins RC:$src1, RC:$src2, x86memop:$src3), let mayLoad = MayLoad in
!strconcat(OpcodeStr, def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>; (ins RC:$src1, RC:$src2, x86memop:$src3),
} // neverHasSideEffects = 1 !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set RC:$dst,
(OpVT (OpNode RC:$src2, RC:$src1,
(mem_frag addr:$src3))))]>;
} }
multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop, multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
ComplexPattern mem_cpat, Intrinsic IntId, ComplexPattern mem_cpat, Intrinsic IntId,
RegisterClass RC, SDNode OpNode, ValueType OpVT> { RegisterClass RC> {
def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst), def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, VR128:$src3), (ins VR128:$src1, VR128:$src2, VR128:$src3),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
@ -274,44 +278,45 @@ multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR128:$dst, [(set VR128:$dst,
(IntId VR128:$src2, VR128:$src1, mem_cpat:$src3))]>; (IntId VR128:$src2, VR128:$src1, mem_cpat:$src3))]>;
def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set RC:$dst,
(OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
let mayLoad = 1 in
def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, RC:$src2, memop:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
} }
} // Constraints = "$src1 = $dst" } // Constraints = "$src1 = $dst"
multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231, multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
string OpStr, Intrinsic IntF32, Intrinsic IntF64, string OpStr, string PackTy, Intrinsic Int,
SDNode OpNode> { SDNode OpNode, RegisterClass RC, ValueType OpVT,
defm SSr132 : fma3s_rm<opc132, !strconcat(OpStr, "132ss"), f32mem, FR32>; X86MemOperand x86memop, Operand memop, PatFrag mem_frag,
defm SSr231 : fma3s_rm<opc231, !strconcat(OpStr, "231ss"), f32mem, FR32>; ComplexPattern mem_cpat> {
defm SDr132 : fma3s_rm<opc132, !strconcat(OpStr, "132sd"), f64mem, FR64>, let neverHasSideEffects = 1 in {
VEX_W; defm r132 : fma3s_rm<opc132, !strconcat(OpStr, !strconcat("132", PackTy)),
defm SDr231 : fma3s_rm<opc231, !strconcat(OpStr, "231sd"), f64mem, FR64>, x86memop, RC, OpVT, mem_frag>;
VEX_W; defm r231 : fma3s_rm<opc231, !strconcat(OpStr, !strconcat("231", PackTy)),
defm SSr213 : fma3s_rm_int <opc213, !strconcat(OpStr, "213ss"), ssmem, x86memop, RC, OpVT, mem_frag>;
sse_load_f32, IntF32, FR32, OpNode, f32>;
defm SDr213 : fma3s_rm_int <opc213, !strconcat(OpStr, "213sd"), sdmem,
sse_load_f64, IntF64, FR64, OpNode, f64>, VEX_W;
} }
defm VFMADD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss, defm r213 : fma3s_rm<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG; x86memop, RC, OpVT, mem_frag, OpNode, 0>,
defm VFMSUB : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss, fma3s_rm_int<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG; memop, mem_cpat, Int, RC>;
}
defm VFNMADD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss, multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG; string OpStr, Intrinsic IntF32, Intrinsic IntF64,
defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss, SDNode OpNode> {
int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG; defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", IntF32, OpNode,
FR32, f32, f32mem, ssmem, loadf32, sse_load_f32>;
defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", IntF64, OpNode,
FR64, f64, f64mem, sdmem, loadf64, sse_load_f64>, VEX_W;
}
defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//