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[Hexagon] Gracefully handle reg class mismatch in HexagonLoopReschedule

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276793 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2016-07-26 19:17:13 +00:00
parent aa3e2e6820
commit a628d047d1
2 changed files with 49 additions and 13 deletions
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32
lib/Target/Hexagon/HexagonBitSimplify.cpp
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@ -2382,8 +2382,8 @@ namespace {
struct PhiInfo {
PhiInfo(MachineInstr &P, MachineBasicBlock &B);
unsigned DefR;
BitTracker::RegisterRef LR, PR;
MachineBasicBlock *LB, *PB;
BitTracker::RegisterRef LR, PR; // Loop Register, Preheader Register
MachineBasicBlock *LB, *PB; // Loop Block, Preheader Block
};
static unsigned getDefReg(const MachineInstr *MI);
@ -2742,31 +2742,37 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
auto F = std::find_if(Phis.begin(), Phis.end(), LoopInpEq);
if (F == Phis.end())
continue;
unsigned PredR = 0;
if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR.Reg, PredR)) {
const MachineInstr *DefPredR = MRI->getVRegDef(F->PR.Reg);
unsigned Opc = DefPredR->getOpcode();
unsigned PrehR = 0;
if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR.Reg, PrehR)) {
const MachineInstr *DefPrehR = MRI->getVRegDef(F->PR.Reg);
unsigned Opc = DefPrehR->getOpcode();
if (Opc != Hexagon::A2_tfrsi && Opc != Hexagon::A2_tfrpi)
continue;
if (!DefPredR->getOperand(1).isImm())
if (!DefPrehR->getOperand(1).isImm())
continue;
if (DefPredR->getOperand(1).getImm() != 0)
if (DefPrehR->getOperand(1).getImm() != 0)
continue;
const TargetRegisterClass *RC = MRI->getRegClass(G.Inp.Reg);
if (RC != MRI->getRegClass(F->PR.Reg)) {
PredR = MRI->createVirtualRegister(RC);
PrehR = MRI->createVirtualRegister(RC);
unsigned TfrI = (RC == &Hexagon::IntRegsRegClass) ? Hexagon::A2_tfrsi
: Hexagon::A2_tfrpi;
auto T = C.PB->getFirstTerminator();
DebugLoc DL = (T != C.PB->end()) ? T->getDebugLoc() : DebugLoc();
BuildMI(*C.PB, T, DL, HII->get(TfrI), PredR)
BuildMI(*C.PB, T, DL, HII->get(TfrI), PrehR)
.addImm(0);
} else {
PredR = F->PR.Reg;
PrehR = F->PR.Reg;
}
}
assert(MRI->getRegClass(PredR) == MRI->getRegClass(G.Inp.Reg));
moveGroup(G, *F->LB, *F->PB, F->LB->getFirstNonPHI(), F->DefR, PredR);
// isSameShuffle could match with PrehR being of a wider class than
// G.Inp.Reg, for example if G shuffles the low 32 bits of its input,
// it would match for the input being a 32-bit register, and PrehR
// being a 64-bit register (where the low 32 bits match). This could
// be handled, but for now skip these cases.
if (MRI->getRegClass(PrehR) != MRI->getRegClass(G.Inp.Reg))
continue;
moveGroup(G, *F->LB, *F->PB, F->LB->getFirstNonPHI(), F->DefR, PrehR);
Changed = true;
}

30
test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll Normal file
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@ -0,0 +1,30 @@
; RUN: llc -march=hexagon < %s
; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
define weak_odr hidden i32 @fred(i32* %this, i32* nocapture readonly dereferenceable(4) %__k) #0 align 2 {
entry:
%call = tail call i64 @danny(i32* %this, i32* nonnull dereferenceable(4) %__k) #2
%__p.sroa.0.0.extract.trunc = trunc i64 %call to i32
br i1 undef, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry
%__p.sroa.0.018 = phi i32 [ %call8, %for.body ], [ %__p.sroa.0.0.extract.trunc, %entry ]
%call8 = tail call i32 @sammy(i32* %this, i32 %__p.sroa.0.018) #2
%0 = inttoptr i32 %call8 to i32*
%lnot.i = icmp eq i32* %0, undef
br i1 %lnot.i, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
ret i32 0
}
declare hidden i64 @danny(i32*, i32* nocapture readonly dereferenceable(4)) #1 align 2
declare hidden i32 @sammy(i32* nocapture, i32) #0 align 2
attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { optsize }