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"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."

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Patch by Kalle Raiskila!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103021 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-05-04 17:58:46 +00:00
parent e9f0fb4179
commit d4ac35b350
2 changed files with 23 additions and 2 deletions
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12
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -941,13 +941,21 @@ SPUDAGToDAGISel::Select(SDNode *N) {
&& ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
&& RN->getReg() != SPU::R1))) { && RN->getReg() != SPU::R1))) {
NewOpc = SPU::Ar32; NewOpc = SPU::Ar32;
Ops[1] = Op1;
if (Op1.getOpcode() == ISD::Constant) { if (Op1.getOpcode() == ISD::Constant) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op1); ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT); Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32); if (isInt<10>(CN->getSExtValue())) {
NewOpc = SPU::AIr32;
Ops[1] = Op1;
} else {
Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILr32, dl,
N->getValueType(0),
Op1),
0);
}
} }
Ops[0] = Op0; Ops[0] = Op0;
Ops[1] = Op1;
n_ops = 2; n_ops = 2;
} }
} }

13
test/CodeGen/CellSPU/storestruct.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llc < %s -march=cellspu | FileCheck %s
%0 = type {i32, i32}
@buffer = global [ 72 x %0 ] zeroinitializer
define void@test( ) {
; Check that there is no illegal "a rt, ra, imm" instruction
; CHECK-NOT: a {{\$., \$., 5..}}
; CHECK: a {{\$., \$., \$.}}
store %0 {i32 1, i32 2} ,
%0* getelementptr ([72 x %0]* @buffer, i32 0, i32 71)
ret void
}