mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-13 23:18:51 +00:00
[mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and II_DIV_D respectively
No functional change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199738 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
be0843e767
commit
fa458d8ad2
@ -1,7 +1,7 @@
|
||||
let isCodeGenOnly = 1, Predicates = [InMicroMips] in {
|
||||
def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
|
||||
ADDS_FM_MM<0, 0x30>;
|
||||
def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>,
|
||||
def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
|
||||
ADDS_FM_MM<0, 0xf0>;
|
||||
def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
|
||||
ADDS_FM_MM<0, 0xb0>;
|
||||
@ -10,7 +10,7 @@ def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
|
||||
|
||||
def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>,
|
||||
ADDS_FM_MM<1, 0x30>;
|
||||
def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, IIFdivDouble, 0, fdiv>,
|
||||
def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>,
|
||||
ADDS_FM_MM<1, 0xf0>;
|
||||
def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>,
|
||||
ADDS_FM_MM<1, 0xb0>;
|
||||
|
@ -422,9 +422,9 @@ let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace="Mips64" in {
|
||||
def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
|
||||
ADDS_FM<0x00, 16>;
|
||||
defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>;
|
||||
def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>,
|
||||
def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
|
||||
ADDS_FM<0x03, 16>;
|
||||
defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
|
||||
defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>;
|
||||
def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
|
||||
ADDS_FM<0x02, 16>;
|
||||
defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
|
||||
|
@ -20,8 +20,6 @@ def IIAlu : InstrItinClass;
|
||||
def IILoad : InstrItinClass;
|
||||
def IIStore : InstrItinClass;
|
||||
def IIBranch : InstrItinClass;
|
||||
def IIFdivSingle : InstrItinClass;
|
||||
def IIFdivDouble : InstrItinClass;
|
||||
def IIFsqrtSingle : InstrItinClass;
|
||||
def IIFsqrtDouble : InstrItinClass;
|
||||
def IIFrecipFsqrtStep : InstrItinClass;
|
||||
@ -52,6 +50,8 @@ def II_DDIV : InstrItinClass;
|
||||
def II_DDIVU : InstrItinClass;
|
||||
def II_DIV : InstrItinClass;
|
||||
def II_DIVU : InstrItinClass;
|
||||
def II_DIV_D : InstrItinClass;
|
||||
def II_DIV_S : InstrItinClass;
|
||||
def II_DMULT : InstrItinClass;
|
||||
def II_DMULTU : InstrItinClass;
|
||||
def II_DROTR : InstrItinClass;
|
||||
@ -225,8 +225,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_MSUB_D , [InstrStage<8, [ALU]>]>,
|
||||
InstrItinData<II_NMADD_D , [InstrStage<8, [ALU]>]>,
|
||||
InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
|
||||
InstrItinData<IIFdivSingle , [InstrStage<23, [ALU]>]>,
|
||||
InstrItinData<IIFdivDouble , [InstrStage<36, [ALU]>]>,
|
||||
InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>,
|
||||
InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
|
||||
InstrItinData<IIFsqrtSingle , [InstrStage<54, [ALU]>]>,
|
||||
InstrItinData<IIFsqrtDouble , [InstrStage<12, [ALU]>]>,
|
||||
InstrItinData<IIFrecipFsqrtStep , [InstrStage<5, [ALU]>]>,
|
||||
|
Loading…
Reference in New Issue
Block a user