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[SystemZ] Avoid generating 2 XOR instructions for (and (xor x, -1), y)

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Summary:
Created a pattern to match 64-bit mode (and (xor x, -1), y)
to a shorter sequence of instructions.

Before the change, the canonical form is translated to:
        xihf    %r3, 4294967295
        xilf    %r3, 4294967295
        ngr     %r2, %r3

After the change, the canonical form is translated to:
        ngr     %r3, %r2
        xgr     %r2, %r3

Reviewers: zhanjunl, uweigand

Subscribers: llvm-commits

Author: assem

Committing on behalf of Assem.

Differential Revision: http://reviews.llvm.org/D21693

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273887 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zhan Jun Liau 2016-06-27 15:55:30 +00:00
parent 339dc3dc8f
commit ff74d2352e
2 changed files with 19 additions and 0 deletions
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5
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -1680,6 +1680,11 @@ def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid,
(i32 63)),
(Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
// Avoid generating 2 XOR instructions. (xor (and x, y), y) is
// equivalent to (and (xor x, -1), y)
def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y),
(XGR GR64:$y, (NGR GR64:$y, GR64:$x))>;
// Peepholes for turning scalar operations into block operations.
defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
XCSequence, 1>;

14
test/CodeGen/SystemZ/and-xor-01.ll Normal file
View File

@ -0,0 +1,14 @@
; Testing peephole for generating shorter code for (and (xor b, -1), a)
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @f1(i64 %a, i64 %b) {
; CHECK-LABEL: f1:
; CHECK: ngr %r3, %r2
; CHECK: xgr %r2, %r3
; CHECK: br %r14
%neg = xor i64 %b, -1
%and = and i64 %neg, %a
ret i64 %and
}