Commit Graph

30 Commits

Author SHA1 Message Date
Hrvoje Varga
6c8d6522ab Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"
This reverts commit r269176 as it caused test-suite failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269287 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 12:46:06 +00:00
Hrvoje Varga
eef2fa80b4 [mips][microMIPS] Implement CFC*, CTC* and LDC* instructions
Differential Revision: http://reviews.llvm.org/D19713


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269176 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-11 12:12:24 +00:00
Zoran Jovanovic
762ad97089 [mips][microMIPS] Revert commit r266861.
Commit r266861 was the reason for failing tests in LLVM test suite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267166 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 16:53:15 +00:00
Hrvoje Varga
6ae2468651 [mips][microMIPS]Implement CFC*, CTC* and LDC* instructions
Differential Revision: http://reviews.llvm.org/D18640


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266861 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-20 06:34:48 +00:00
Zlatko Buljan
4e6485e747 [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions
Differential Revision: http://reviews.llvm.org/D17334


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265002 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-31 08:51:24 +00:00
Hrvoje Varga
405224b9ee [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions
Differential Revision: http://reviews.llvm.org/D17328


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264246 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 08:02:09 +00:00
Hrvoje Varga
c309d73346 [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt
Differential Revision: http://reviews.llvm.org/D13885


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254405 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-01 11:59:21 +00:00
Daniel Sanders
3c6d533372 [mips][sched] Split IIBranch into specific instruction classes.
Summary:
Almost no functional change since the InstrItinData's have been duplicated.
The one functional change is to remove IIBranch from the MSA branches. The
classes will be assigned to the MSA instructions as part of implementing
the P5600 scheduler.

II_IndirectBranchPseudo and II_ReturnPseudo can probably be removed. I've
preserved the itinerary information for the corresponding pseudo
instructions to avoid making a functional change to these pseudos in
this patch.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12189


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248273 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 13:36:28 +00:00
Zoran Jovanovic
11768ab081 [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions
Differential Revision: http://reviews.llvm.org/D11674


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246968 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-07 13:01:04 +00:00
Toma Tabacu
3fdd82e066 [mips] Only use FGR_{32,64} in TableGen descriptions. NFC.
Summary: Instead of explicitly adding the IsFP64bit and NotFP64bit predicates through AdditionalRequires.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9566

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236835 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 12:15:04 +00:00
Jozef Kolek
9fece51399 [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.
Differential Revision: http://reviews.llvm.org/D6169


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222355 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 13:37:51 +00:00
Daniel Sanders
1f4c755c2c [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6
Summary:
Also tightened up the acceptable condition operand for these instructions
on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior
to that only $fcc0 is acceptable.

We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's
probably best to do this in InstCombine.

Depends on D4111

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4112

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210787 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 15:00:17 +00:00
Daniel Sanders
28002c2f82 [mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6
Summary:
Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in
mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed
by getelementptr). This does not affect the purpose of the test.

Depends on D4004

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4110

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210784 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 14:19:28 +00:00
Daniel Sanders
0e0f907356 [mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-3 that was available in MIPS32R2.

To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are tested.

rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.

Depends on D3696

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208690 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 11:45:36 +00:00
Daniel Sanders
31546cd352 [mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-V that was available in MIPS32R2

Most of these instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now. It happens
because many of the MIPS V instructions have not been implemented.

Depends on D3694

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208546 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 12:52:44 +00:00
Daniel Sanders
a3953a30b6 [mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
The overall idea is to chop the Predicates list into subsets that are
usually overridden independently. This allows subclasses to partially
override the predicates of their superclasses without having to re-add all
the existing predicates.

This patch starts the process by moving HasStdEnc into a new
EncodingPredicates list and almost everything else into
AdditionalPredicates.

It has revealed a couple likely bugs where 'let Predicates' has removed
the HasStdEnc predicate.

No functional change (confirmed by diffing tablegen-erated files).

Depends on D3549, D3506

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3550

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208184 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:27:09 +00:00
Daniel Sanders
0c9ea21554 [mips] Move HasStdEnc to the front of the predicates lists.
Summary:
This will make it easier to prove that a more complicated change in the
following commit is non-functional.

No functional change.

Depends on D3506

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3549

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208179 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 09:58:05 +00:00
Daniel Sanders
2b9c11c071 [mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199748 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 15:03:52 +00:00
Daniel Sanders
49671f1b1a [mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199747 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 14:50:20 +00:00
Daniel Sanders
dc5734786a [mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1
No functional change since the InstrItinData's have been duplicated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 13:59:56 +00:00
Daniel Sanders
faacfecf60 [mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and II_SQRT_D respectively
No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199741 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 13:36:45 +00:00
Daniel Sanders
fa458d8ad2 [mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and II_DIV_D respectively
No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199738 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 13:22:08 +00:00
Daniel Sanders
be0843e767 [mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199737 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 13:07:31 +00:00
Daniel Sanders
c55cf21ac0 [mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199734 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 12:51:44 +00:00
Daniel Sanders
b029a0ec6a [mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS]
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 12:38:07 +00:00
Daniel Sanders
65d38c3fcd [mips][sched] Split IIFcmp into II_C_CC_[SD]
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199728 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 11:42:48 +00:00
Daniel Sanders
0e65e8c2a7 [mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD]
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199727 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 11:28:03 +00:00
Daniel Sanders
c2e835fd7e [mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199722 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 10:56:23 +00:00
Zoran Jovanovic
ae3597c141 Support for microMIPS FPU instructions 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 10:09:27 +00:00
Zoran Jovanovic
1ef2ca6994 Support for microMIPS FPU instructions 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-20 15:44:08 +00:00