26904 Commits

Author SHA1 Message Date
Duncan P. N. Exon Smith
fb23bd1e2e ValueMapper: clang-format ValueMapper.h, NFC
Also remove duplicated identifiers from comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265611 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 22:37:30 +00:00
Peter Zotov
2a41371ff7 [llvm-c] Add LLVMGetValueKind.
Patch by Nicole Mazzuca <npmazzuca@gmail.com>.

Differential Revision: http://reviews.llvm.org/D18729

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265608 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 22:21:29 +00:00
Kevin Enderby
c6bf9be16d Thread Expected<...> up from createMachOObjectFile() to allow llvm-objdump to produce a real error message
Produce the first specific error message for a malformed Mach-O file describing
the problem instead of the generic message for object_error::parse_failed of
"Invalid data was encountered while parsing the file”.  Many more good error
messages will follow after this first one.

This is built on Lang Hames’ great work of adding the ’Error' class for
structured error handling and threading Error through MachOObjectFile
construction.  And making createMachOObjectFile return Expected<...> .

So to to get the error to the llvm-obdump tool, I changed the stack of
these methods to also return Expected<...> :

  object::ObjectFile::createObjectFile()
  object::SymbolicFile::createSymbolicFile()
  object::createBinary()

Then finally in ParseInputMachO() in MachODump.cpp the error can
be reported and the specific error message can be printed in llvm-objdump
and can be seen in the existing test case for the existing malformed binary
but with the updated error message.

Converting these interfaces to Expected<> from ErrorOr<> does involve
touching a number of places. To contain the changes for now use of
errorToErrorCode() and errorOrToExpected() are used where the callers
are yet to be converted.

Also there some were bugs in the existing code that did not deal with the
old ErrorOr<> return values.  So now with Expected<> since they must be
checked and the error handled, I added a TODO and a comment:
“// TODO: Actually report errors helpfully” and a call something like
consumeError(ObjOrErr.takeError()) so the buggy code will not crash
since needed to deal with the Error.

Note there is one fix also needed to lld/COFF/InputFiles.cpp that goes along
with this that I will commit right after this.  So expect lld not to built
after this commit and before the next one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265606 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 22:14:09 +00:00
Quentin Colombet
d50171b8c7 [RegisterBankInfo] Add methods to get the possible mapping of an instruction on a register bank.
This will be used by the register bank select pass to assign register banks
for generic virtual registers.

This was originally committed as r265573 but broke at least one windows bot.
The problem with the windows bot was that it was using a copy constructor for
the InstructionMappings class and could not synthesize it. Actually, the fact
that this class is not copy constructable is expected and the compiler should
use the move assignment constructor. Marking the problematic assignment
explicitly as using the move constructor has its own problems.

Indeed, with recent clang we get a warning that we may prevent the elision of
the copy by the compiler. A proper fix for both compilers would be to change the
API of getPossibleInstrMapping to take a InstructionMappings as input/output
parameter. This does not feel natural and since GISel is not used on windows
yet, I chose to workaround the problem by not compiling the problematic code on
windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265604 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 21:37:22 +00:00
JF Bastien
b36d1a86f1 NFC: make AtomicOrdering an enum class
Summary:
In the context of http://wg21.link/lwg2445 C++ uses the concept of
'stronger' ordering but doesn't define it properly. This should be fixed
in C++17 barring a small question that's still open.

The code currently plays fast and loose with the AtomicOrdering
enum. Using an enum class is one step towards tightening things. I later
also want to tighten related enums, such as clang's
AtomicOrderingKind (which should be shared with LLVM as a 'C++ ABI'
enum).

This change touches a few lines of code which can be improved later, I'd
like to keep it as NFC for now as it's already quite complex. I have
related changes for clang.

As a follow-up I'll add:
  bool operator<(AtomicOrdering, AtomicOrdering) = delete;
  bool operator>(AtomicOrdering, AtomicOrdering) = delete;
  bool operator<=(AtomicOrdering, AtomicOrdering) = delete;
  bool operator>=(AtomicOrdering, AtomicOrdering) = delete;
This is separate so that clang and LLVM changes don't need to be in sync.

Reviewers: jyknight, reames

Subscribers: jyknight, llvm-commits

Differential Revision: http://reviews.llvm.org/D18775

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265602 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 21:19:33 +00:00
Nicolai Haehnle
ea7a0c0467 AMDGPU: Add a shader calling convention
This makes it possible to distinguish between mesa shaders
and other kernels even in the presence of compute shaders.

Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

Differential Revision: http://reviews.llvm.org/D18559

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265589 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 19:40:20 +00:00
Quentin Colombet
e09831206a Revert "[RegisterBankInfo] Add methods to get the possible mapping of an
instruction on a register bank. This will be used by the register bank select
pass to assign register banks for generic virtual registers." and the follow-on
commits while I find out a way to fix the win7 bot:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/19882

This reverts commit r265578, r265581, r265584, and r265585.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265587 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 19:04:58 +00:00
Quentin Colombet
0fad13dc00 [RegisterBankInfo] Get rid of the assert in the constructor of InstructionMapping.
The default constructor now uses the regular constructor and the assert
is not valid anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265585 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 18:43:46 +00:00
Quentin Colombet
d030a6cdd9 [RegisterBankInfo] Call the other constructor of InstructionMapping from the
default constructor, instead of relying on the default constructor of
unique_ptr.

Second attempt at fixing the windows bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265584 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 18:37:44 +00:00
Evgeniy Stepanov
d8c5d5c30e [gold] Save bitcode for module partitions (save-temps + split codegen).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265583 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 18:32:13 +00:00
Quentin Colombet
fe58f90a22 [RegisterBankInfo] Provide a default constructor for InstructionMapping
helper class.

The default constructor creates invalid (isValid() == false) instances
and may be used to communicate that a mapping was not found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265581 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 18:24:34 +00:00
Duncan P. N. Exon Smith
a15c0e9ce0 IR: Use DenseSet instead of DenseMap for ConstantUniqueMap; NFC
Use a DenseSet instead of a DenseMap for constants in LLVMContextImpl.
Last time I looked at this was some time before r223588, when
DenseSet<V> had no advantage over DenseMap<V,char>.  After r223588,
there's a 50% memory savings.

This is all mechanical.  There were little bits of missing API from
DenseSet so I added the trivial implementations:

  - iterator::operator++(int)
  - template <class LookupKeyT> insert_as(ValueTy, LookupKeyT)

There should be no functionality change, just reduced memory consumption
(this wasn't on a profile or anything; just a cleanup I stumbled on).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265577 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 17:56:08 +00:00
Quentin Colombet
b5dd9acfff [RegisterBankInfo] Add a method to get the mapping RegClass -> RegBank.
This should be TableGen'ed at some point.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265574 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 17:51:41 +00:00
Quentin Colombet
4bbf81ac57 [RegisterBankInfo] Add methods to get the possible mapping of an instruction on a register bank.
This will be used by the register bank select pass to assign register banks
for generic virtual registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265573 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 17:45:40 +00:00
Quentin Colombet
12ea314247 [RegisterBankInfo] Make the destructor public... that may be useful!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265565 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 17:09:34 +00:00
Quentin Colombet
e33ae0279e [RegisterBankInfo] Implement the verify method of the InstructionMapping helper class.
This checks that all the register operands get a proper mapping.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265563 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 17:01:43 +00:00
Fiona Glaser
a4b0d0e4db Loop Unroll: add options and tweak to make Partial unrolling more useful
1. Add FullUnrollMaxCount option that works like MaxCount, but also limits
   the unroll count for fully unrolled loops. So if a loop has an iteration
   count over this, it won't fully unroll.
2. Add CLI options for MaxCount and the new option, so they can be tested
   (plus a test).
3. Make partial unrolling obey MaxCount.

An example use-case (the out of tree one this is originally designed for) is
a target’s TTI can analyze a loop and decide on a max unroll count separate
from the size threshold, e.g. based on register pressure, then constrain
LoopUnroll to not exceed that, regardless of the size of the unrolled loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265562 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 16:57:25 +00:00
Quentin Colombet
a80c06540f [MachineRegisterInfo] Document what is the expected metric for the size of generic registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265561 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 16:51:04 +00:00
Quentin Colombet
560a956259 [RegisterBankInfo] Implement the verify method for the ValueMapping helper class.
The method checks that the value is fully defined accross the different partial
mappings and that the partial mappings are compatible between each other.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265556 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 16:40:23 +00:00
Quentin Colombet
6f5e1e215f [RegisterBankInfo] Add a verify method for the PartialMapping helper class.
This verifies that the PartialMapping can be accomadated into the related
register bank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265555 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 16:33:26 +00:00
Quentin Colombet
67f02253c9 [RegisterBankInfo] Add a couple of helper classes for the future cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265553 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 16:27:01 +00:00
Quentin Colombet
bc6e9634c0 [RegisterBankInfo] Inline the destructor to avoid link-time error when GlobalISel is not built.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265548 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 15:47:17 +00:00
Wei Mi
1145b58255 Recommit r265309 after fixed an invalid memory reference bug happened
when DenseMap growed and moved memory. I verified it fixed the bootstrap
problem on x86_64-linux-gnu but I cannot verify whether it fixes
the bootstrap error on clang-ppc64be-linux. I will watch the build-bot
result closely.

Replace analyzeSiblingValues with new algorithm to fix its compile
time issue. The patch is to solve PR17409 and its duplicates.

analyzeSiblingValues is a N x N complexity algorithm where N is
the number of siblings generated by reg splitting. Although it
causes siginificant compile time issue when N is large, it is also
important for performance since it removes redundent spills and
enables rematerialization.

To solve the compile time issue, the patch removes analyzeSiblingValues
and replaces it with lower cost alternatives containing two parts. The
first part creates a new spill hoisting method in postOptimization of
register allocation. It does spill hoisting at once after all the spills
are generated instead of inside every instance of selectOrSplit. The
second part queries the define expr of the original register for
rematerializaiton and keep it always available during register allocation
even if it is already dead. It deletes those dead instructions only in
postOptimization. With the two parts in the patch, it can remove
analyzeSiblingValues without sacrificing performance.

Differential Revision: http://reviews.llvm.org/D15302


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265547 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 15:41:07 +00:00
Silviu Baranga
89e8236bfb Revert r265535 until we know how we can fix the bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265541 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 14:06:32 +00:00
Silviu Baranga
39fbde60e1 [SCEV] Introduce a guarded backedge taken count and use it in LAA and LV
Summary:
When the backedge taken codition is computed from an icmp, SCEV can
deduce the backedge taken count only if one of the sides of the icmp
is an AddRecExpr. However, due to sign/zero extensions, we sometimes
end up with something that is not an AddRecExpr.

However, we can use SCEV predicates to produce a 'guarded' expression.
This change adds a method to SCEV to get this expression, and the
SCEV predicate associated with it.

In HowManyGreaterThans and HowManyLessThans we will now add a SCEV
predicate associated with the guarded backedge taken count when the
analyzed SCEV expression is not an AddRecExpr. Note that we only do
this as an alternative to returning a 'CouldNotCompute'.

We use new feature in Loop Access Analysis and LoopVectorize to analyze
and transform more loops.

Reviewers: anemet, mzolotukhin, hfinkel, sanjoy

Subscribers: flyingforyou, mcrosier, atrick, mssimpso, sanjoy, mzolotukhin, llvm-commits

Differential Revision: http://reviews.llvm.org/D17201

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265535 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 13:18:26 +00:00
Duncan P. N. Exon Smith
e49dfa7e9a IRMover: Steal arguments when moving functions, NFC
Instead of copying arguments from the source function to the
destination, steal them.  This has a few advantages.

  - The ValueMap doesn't need to be seeded with (or cleared of)
    Arguments.

  - Often the destination function won't have created any arguments yet,
    so this avoids malloc traffic.

  - Argument names don't need to be copied.

Because argument lists are lazy, this required a new
Function::stealArgumentListFrom helper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265519 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 06:38:15 +00:00
Matthias Braun
dc2f859a3f RegisterScavenger: Take a reference as enterBasicBlock() argument.
Make it obvious that the argument cannot be nullptr.
Remove an unnecessary nullptr check in initRegState.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265511 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 02:47:09 +00:00
Matthias Braun
72b4fa0d1c LivePhysRegs: removeReg() must remove aliased registers
We must remove all aliased registers which may be more than the all sub
and super registers combined.

Bug found while reading the code. The bug does not affect any existing
target as the only use of register aliases I could found were control
registers on ARM and Hexagon which are all reserved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265510 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 02:46:35 +00:00
Quentin Colombet
c37faf21d0 [RegisterBankInfo] Include RegisterBank.h.
We actually need the definition of a RegisterBank to be able to inline
the implementation of the subscript operator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265492 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:57:25 +00:00
Quentin Colombet
717601810e [RegisterBankInfo] Add missing include for assert.
This should appease the linux bot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265491 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:43:58 +00:00
Quentin Colombet
6443af0d08 [RegisterBankInfo] Simplify the API for build a register bank.
As part of the TRI argument of addRegBankCoverage we already have access to
the TargetRegisterClass through the ID of that register class.
Therefore, there is no point in needing a TargetRegisterClass instance,
the ID is enough to get to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265487 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:26:39 +00:00
Quentin Colombet
5a3e3ec846 [Target] Remove a deprecated comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265484 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:04:54 +00:00
Quentin Colombet
ca7369ade3 [Target] Add an accessor to the register bank information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265483 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 22:50:40 +00:00
Evgeniy Stepanov
9c4431f3cb Faster stack-protector for Android/AArch64.
Bionic has a defined thread-local location for the stack protector
cookie. Emit a direct load instead of going through __stack_chk_guard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265481 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 22:41:50 +00:00
Quentin Colombet
6077d14b60 [RegisterBank] Add printable capabilities for future debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265473 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:40:43 +00:00
Quentin Colombet
ccd741b08a [RegisterBankInfo] Make addRegBankCoverage more capable to ease
targeting jobs.
Now, addRegBankCoverage also adds the subreg-classes not just the
sub-classes of the given register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265469 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:20:12 +00:00
Duncan P. N. Exon Smith
d7773c0d39 IR: Introduce ConstantAggregate, NFC
Add a common parent class for ConstantArray, ConstantVector, and
ConstantStruct called ConstantAggregate.  These are the aggregate
subclasses of Constant that take operands.

This is mainly a cleanup, adding common `isa` target and removing
duplicated code.  However, it also simplifies caching which constants
point transitively at `GlobalValue` (a possible future direction).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265466 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:10:45 +00:00
Quentin Colombet
062bf7c9dd [RegisterBankInfo] Implement the methods to create register banks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265464 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:06:15 +00:00
Quentin Colombet
aa40fb64ae [RegisterBank] Provide a way to check if a register bank is valid.
Change the default constructor to create invalid object.
The target will have to properly initialize the register banks before
using them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265460 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 20:48:32 +00:00
Duncan P. N. Exon Smith
f45d3278d3 Make constructors for final subclasses of Constant private, NFC
These were `protected` before, but might as well be `private`.  Also
marked the classes themselves `final`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265458 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 20:31:23 +00:00
Quentin Colombet
cdf87d0168 [TargetRegisterClass] Improve the comment for how to use getSubClassMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265455 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 20:21:53 +00:00
Quentin Colombet
baea9b2a9a [GlobalISel] Add the RegisterBankInfo class for the handling of register banks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265449 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 20:02:47 +00:00
Lang Hames
c224d81083 [Support] Add a checked flag to Expected<T>, require checks before access or
destruction.

This makes the Expected<T> class behave like Error, even when in success mode.
Expected<T> values must be checked to see whether they contain an error prior
to being dereferenced, assigned to, or destructed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265446 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 19:57:03 +00:00
Quentin Colombet
9b710764b9 [GlobalISel] Add a class, RegisterBank, to represent register banks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265445 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 19:54:44 +00:00
Quentin Colombet
278bb5de48 [GlobalISel] Add the skeleton of the RegBankSelect pass.
This pass is reponsible for assigning the generic virtual registers to register
banks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265440 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 19:06:01 +00:00
Lang Hames
8a1ae616c9 [Support] clang-format Error.h.
This tidies up the ExitOnError class and some other recently added code. NFC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265438 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 18:50:09 +00:00
Manman Ren
2bf0ebe961 Swift Calling Convention: swifterror target-independent change.
At IR level, the swifterror argument is an input argument with type
ErrorObject**. For targets that support swifterror, we want to optimize it
to behave as an inout value with type ErrorObject*; it will be passed in a
fixed physical register.

The main idea is to track the virtual registers for each swifterror value. We
define swifterror values as AllocaInsts with swifterror attribute or a function
argument with swifterror attribute.

In SelectionDAGISel.cpp, we set up swifterror values (SwiftErrorVals) before
handling the basic blocks.

When iterating over all basic blocks in RPO, before actually visiting the basic
block, we call mergeIncomingSwiftErrors to merge incoming swifterror values when
there are multiple predecessors or to simply propagate them. There, we create a
virtual register for each swifterror value in the entry block. For predecessors
that are not yet visited, we create virtual registers to hold the swifterror
values at the end of the predecessor. The assignments are saved in
SwiftErrorWorklist and will be materialized at the end of visiting the basic
block.

When visiting a load from a swifterror value, we copy from the current virtual
register assignment. When visiting a store to a swifterror value, we create a
virtual register to hold the swifterror value and update SwiftErrorMap to
track the current virtual register assignment.

Differential Revision: http://reviews.llvm.org/D18108


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265433 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 18:13:16 +00:00
Rafael Espindola
00d9a04525 Use ArrayRef for contiguous areas in ELF. NFC.
This just simplifies the code a bit. More so in lld.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265403 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 14:47:22 +00:00
Rafael Espindola
c5c3d28dda Centralize the definition of a few types. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265399 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 14:10:18 +00:00
Peter Zotov
2b8aed70d6 [llvm-c] Expose LLVM{Get,Set}ModuleIdentifier
Patch by Nicole Mazzuca <npmazzuca@gmail.com>.

Differential Revision: http://reviews.llvm.org/D18736

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265394 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 13:56:59 +00:00