RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-03 01:12:59 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
60,833 Commits 27 Branches 0 Tags 473 MiB
29e7e32e08
Commit Graph

621 Commits

Author SHA1 Message Date
Bob Wilson
5e2b05a71e Delete dead PHI machine instructions. These can be created due to type 
legalization even when the IR-level optimizer has removed dead phis, such
as when the high half of an i64 value is unused on a 32-bit target.
I had to adjust a few test cases that had dead phis.
This is a partial fix for Radar 7627077.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95816 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-10 22:58:57 +00:00
Chris Lattner
d863b766f5 convert to filecheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-08 23:47:34 +00:00
Evan Cheng
00a99a3584 Run codegen dce pass for all targets at all optimization levels. Previously it's 
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95493 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-06 09:07:11 +00:00
Anton Korobeynikov
90cfc130d6 Fix a gross typo: ARMv6+ may or may not support unaligned memory operations. 
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).

Allow unaligned memops on darwin and conservatively disallow them otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-30 14:08:12 +00:00
Chris Lattner
c618c8aff4 emit jump table an alias ".set" directives through MCStreamer as 
assignments.

.set x, a-b

is the same as:

x = a-b



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94596 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-26 21:53:08 +00:00
Rafael Espindola
2e2563bf8e Emit .comm alignment in bytes but .align in powers of 2 for ARM ELF. 
Original patch by Sandeep Patel and updated by me.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-26 20:21:43 +00:00
Rafael Espindola
0173b74c55 Update test for darwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-25 15:32:10 +00:00
Rafael Espindola
f166ed7324 Fix PR6134. 
We are not emitting alignments on Darwin for "bar". Not sure what is the
correct way to do it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94400 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-25 02:27:39 +00:00
Dan Gohman
7979b72feb Revert LoopStrengthReduce.cpp to pre-r94061 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94123 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-22 00:46:49 +00:00
Dan Gohman
a10756ee65 Re-implement the main strength-reduction portion of LoopStrengthReduction. 
This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.

It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94061 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-21 02:09:26 +00:00
Evan Cheng
f06c28aac4 Test case for r93758. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93824 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-19 00:35:20 +00:00
Bob Wilson
3a4a832223 The Neon "vtst" instruction takes a suffix that is the element size alone -- 
adding an "i" to the suffix, indicating that the elements are integers, is
accepted but not part of the standard syntax.  This helps us pass a few more
of the Neon tests from gcc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-17 06:35:17 +00:00
Bob Wilson
516ab96de3 Run the pre-register allocation tail duplication pass by default. Remove 
the -pre-regalloc-taildup command-line option, and add a new
-disable-early-taildup option.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93597 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-16 00:29:50 +00:00
Chris Lattner
2f8cc26be4 remove uses of deprecated functions, this generates slightly 
different BlockAddress labels, but nothing semantically important.

Add a FIXME that BlockAddress codegen is broken if the LLVM BB has 
an empty name (e.g. strip was run).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93303 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-13 07:30:49 +00:00
Dan Gohman
aceba31b7a Delete useless trailing semicolons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 17:55:26 +00:00
Chris Lattner
0fba8cf9ff Make this more likely to generate a libcall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92387 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-01 03:26:51 +00:00
Bob Wilson
5afffaed5c Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 01:03:29 +00:00
Evan Cheng
d831cda3e7 - Support inline asm 'w' constraint for 128-bit vector types. 
- Also support the 'q' NEON registers asm code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-08 23:06:22 +00:00
Bob Wilson
324f4f1633 Recognize canonical forms of vector shuffles where the same vector is used for 
both source operands.  In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand.  Radar 7434842.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90417 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-03 06:40:55 +00:00
Evan Cheng
a4025df42d Fix PR5614: parts of a physical register def may be killed the rest. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90180 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-01 00:44:45 +00:00
Anton Korobeynikov
5cdc3a949a Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-24 00:44:37 +00:00
Jim Grosbach
77b02beb1f move fconst[sd] to UAL. <rdar://7414913> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89700 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 21:08:25 +00:00
Edward O'Callaghan
11cc4fab52 Convert ARM tests to FileCheck for PR5307. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89593 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-22 14:23:33 +00:00
Edward O'Callaghan
de9b6b1cd5 Forgot to alter RUN line when converting to FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89588 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-22 13:09:48 +00:00
Edward O'Callaghan
85d1aab444 Fix for bad FileCheck converts in revision 89584. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89586 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-22 12:50:05 +00:00
Edward O'Callaghan
81fff07daf Convert a few tests to FileCheck for PR5307. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89584 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-22 11:45:44 +00:00
Jim Grosbach
21ce2e3c74 Revert 89562. We're being sneakier than I was giving us credit for, and this 
isn't necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89568 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-21 23:34:09 +00:00
Jim Grosbach
f3b33d0b2a Darwin requires a frame pointer for all non-leaf functions to support correct 
backtraces.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89562 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-21 21:40:08 +00:00
Evan Cheng
4aedb61d03 Remat VLDRD from constpool. Clean up some instruction property specifications. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 19:57:15 +00:00
Evan Cheng
9ef4835bd8 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89423 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 00:54:03 +00:00
Bob Wilson
41a0456a3c Fix buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89274 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-18 23:30:38 +00:00
Bob Wilson
60f34b9fb0 Tail duplication still needs to iterate. Duplicating new instructions onto 
the tail of a block may make that block a new candidate for duplication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89264 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-18 22:52:37 +00:00
Anton Korobeynikov
d2aad77261 Forgot to commit test fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89138 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 20:38:36 +00:00
Jim Grosbach
a44321776e Detect need for autoalignment of the stack earlier to catch spills more 
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-15 21:45:34 +00:00
Evan Cheng
d57cdd5683 - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-14 02:55:43 +00:00
Evan Cheng
e17ae4f82e Add radar number. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88739 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-14 02:11:32 +00:00
Evan Cheng
8fdd84cfa7 Fix PR5412: Fix an inverted check and another missing sub-register check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88738 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-14 02:09:09 +00:00
Evan Cheng
1f6a3c820a Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88719 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-13 23:16:41 +00:00
Evan Cheng
236490d870 Fix PR5410: LiveVariables lost subreg def: 
D0<def,dead> = ...
...
             = S0<use, kill>
S0<def>      = ...
...
D0<def>      = 

The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88690 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-13 20:36:40 +00:00
Jim Grosbach
e5165490b7 Use Unified Assembly Syntax for the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 00:11:35 +00:00
Anton Korobeynikov
e8ea011cc7 It turns out that the testcase in question uncovered subreg-handling bug. 
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86375 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 15:20:32 +00:00
Anton Korobeynikov
fc2cba8362 Honour subreg machine operands during asmprinting 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86303 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:45:15 +00:00
Bob Wilson
54c78ef2fe Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86301 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:33:28 +00:00
Evan Cheng
e7e0d62efd Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86294 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 22:24:13 +00:00
Dan Gohman
3f131328ff Update these tests for the new label names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86192 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 23:31:40 +00:00
Bob Wilson
8a008cc49d Attempt again to fix buildbot failures: make expected output less specific 
and compile with -mtriple to specify *-apple-darwin targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 00:30:35 +00:00
Bob Wilson
1709dd73d6 Fix broken test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86045 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 20:04:11 +00:00
Bob Wilson
0d48d6106e Add test for ARM indirectbr codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 19:25:34 +00:00
Evan Cheng
b23b2015eb fconsts / fconstd immediate should be proceeded with #. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85952 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 21:59:33 +00:00
Evan Cheng
777c6b7caa Re-apply 85799. It turns out my code isn't buggy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85947 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 21:40:02 +00:00
Evan Cheng
ba908640b3 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:52:54 +00:00
Anton Korobeynikov
ab453e0641 Revert r85049, it is causing PR5367 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85847 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 00:24:48 +00:00
Evan Cheng
454ac8961b Revert 85799 for now. It might be breaking llvm-gcc driver. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85827 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 21:49:14 +00:00
Evan Cheng
72ed88feac Initilize the machine LICM CSE map upon the first time an instruction is hoisted to 
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85799 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 08:09:49 +00:00
Evan Cheng
580e791ded Remove an irrelevant and poorly reduced test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85794 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 07:11:54 +00:00
Anton Korobeynikov
2ae0eec1c0 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
2e1da9fea4 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85765 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:06 +00:00
Jim Grosbach
8cd0a8cb82 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 22:57:36 +00:00
Jim Grosbach
07d236ba88 Update test to be more explicit about what instruction sequences are expected for each operation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85689 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:52:58 +00:00
Jim Grosbach
bcf2f2c159 Expand 64-bit logical shift right inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:42:19 +00:00
Jim Grosbach
b4a976c304 Expand 64-bit arithmetic shift right inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:00:56 +00:00
Jim Grosbach
c2b879fcfe Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 19:38:01 +00:00
Benjamin Kramer
823bdbc770 Add missing colons for FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85674 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 19:22:24 +00:00
Jim Grosbach
4a26092248 Convert to FileCheck 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85673 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 19:06:53 +00:00
Rafael Espindola
c1382b745f This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 14:33:14 +00:00
Evan Cheng
39382427f1 Use fconsts and fconstd to materialize small fp constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 01:44:26 +00:00
Rafael Espindola
2bda533e1c Add missing testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85266 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 17:59:03 +00:00
Bob Wilson
b9350315d2 Fix the rest of the ARM failures by converting them to FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85208 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 06:16:45 +00:00
Bob Wilson
13e80bdb71 Fix some more failures by converting to FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85207 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 05:50:28 +00:00
Bob Wilson
8bb080e71b Convert to FileCheck, fixing failure due to tab change in the process. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85204 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 05:30:47 +00:00
Evan Cheng
cc7a5b91de Update tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85050 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 07:53:48 +00:00
Bob Wilson
bac6ed4ba4 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 16:52:21 +00:00
Evan Cheng
87689d3b70 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 06:48:32 +00:00
Evan Cheng
8000c6c535 Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 00:40:00 +00:00
Evan Cheng
2095659a85 Match more patterns to movt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 08:15:52 +00:00
Anton Korobeynikov
2bcf60a9cc Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign) 
transform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84683 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 21:37:45 +00:00
Chris Lattner
7bf4bc5a1d convert to filecheck syntax and make a lot more aggressive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:27:56 +00:00
Chris Lattner
baa989ed6e rename test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84515 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:18:07 +00:00
Evan Cheng
d3dd50fec0 Enable post-alloc scheduling for all ARM variants except for Thumb1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 06:11:08 +00:00
Bob Wilson
765cc0b9d5 Revise ARM inline assembly memory operands to require the memory address to 
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84022 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 20:50:28 +00:00
Sandeep Patel
47eedaa8fa Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 18:59:48 +00:00
Benjamin Kramer
90869455b5 Eliminate some redundant llvm-as calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83837 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-12 09:31:55 +00:00
Dan Gohman
cda49a0b29 Update this test; the code is the same but it gets counted as one 
fewer remat.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83690 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 23:31:04 +00:00
Bob Wilson
83815aeb29 Merge a bunch of NEON tests into larger files so they run faster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83667 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 20:20:54 +00:00
Bob Wilson
e8e72be33a Convert some ARM tests with lots of greps to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83651 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 17:20:46 +00:00
Bob Wilson
8795070d50 Commit one last NEON test to use FileCheck. That's all of them now! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83617 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 05:31:56 +00:00
Bob Wilson
0305dd745e Convert more NEON tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83616 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 05:14:48 +00:00
Bob Wilson
5631139a69 Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 00:01:36 +00:00
Bob Wilson
8cdb269686 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 23:51:31 +00:00
Bob Wilson
c5c6edb74f Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83596 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 23:38:24 +00:00
Bob Wilson
4cf0189d5a Convert more NEON tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83595 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 23:33:03 +00:00
Bob Wilson
62e053e5a1 Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83590 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 22:53:57 +00:00
Bob Wilson
5d78275493 Convert more NEON tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83587 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 22:33:53 +00:00
Bob Wilson
0bf7d998b4 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 22:27:33 +00:00
Anton Korobeynikov
632606c724 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83572 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 20:43:22 +00:00
Bob Wilson
30aea9d96e Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 18:56:10 +00:00
Bob Wilson
67a6103a34 Convert more NEON tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83528 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 06:02:10 +00:00
Bob Wilson
deb3141cf5 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 05:18:18 +00:00
Bob Wilson
5adf60c03b Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:28:28 +00:00
Bob Wilson
24e04c535f Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:21:01 +00:00