Commit Graph

40691 Commits

Author SHA1 Message Date
Vyacheslav Klochkov
35cecc31aa Fixed the lost FastMathFlags for FCmp operations in SLPVectorizer.
Reviewer: Michael Zolotukhin.
Differential Revision: https://reviews.llvm.org/D26543


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286626 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 19:55:29 +00:00
Sanjay Patel
a27bda70c2 [InstCombine] add tests to show size-increasing select transforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286619 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 19:37:54 +00:00
Chad Rosier
687ce7f4a1 [AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286617 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 19:25:48 +00:00
Geoff Berry
beb51d459e [AArch64] Fix bugs in isel lowering replaceSplatVectorStore.
Summary:
Fix off-by-one indexing error in loop checking that inserted value was a
splat vector.

Add code to check that INSERT_VECTOR_ELT nodes constructing the splat
vector have the expected constant index values.

Reviewers: t.p.northover, jmolloy, mcrosier

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D26409

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286616 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 19:25:20 +00:00
Evgeniy Stepanov
81323af362 [cfi] Implement cfi-icall using inline assembly.
The current implementation is emitting a global constant that happens
to evaluate to the same bytes + relocation as a jump instruction on
X86. This does not work for PIE executables and shared libraries
though, because we end up with a wrong relocation type. And it has no
chance of working on ARM/AArch64 which use different relocation types
for jump instructions (R_ARM_JUMP24) that is never generated for
data.

This change replaces the constant with module-level inline assembly
followed by a hidden declaration of the jump table. Works fine for
ARM/AArch64, but has some drawbacks.
* Extra symbols are added to the static symbol table, which inflate
the size of the unstripped binary a little. Stripped binaries are not
affected. This happens because jump table declarations must be
external (because their body is in the inline asm).
* Original functions that were anonymous are now named
<original name>.cfi, and it affects symbolization sometimes. This is
necessary because the only user of these functions is the (inline
asm) jump table, so they had to be added to @llvm.used, which does
not allow unnamed functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286611 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 18:49:09 +00:00
Adrian Prantl
ec6378facd Revert "Use private linkage for MergedGlobals variables" on Darwin.
This is a partial revert of r244615 (http://reviews.llvm.org/D11942),
which caused a major regression in debug info quality.

Turning the artificial __MergedGlobal symbols into private symbols
(l__MergedGlobal) means that the linker will not include them in the
symbol table of the final executable. Without a symbol table entry
dsymutil is not be able to process the debug info for any of the
merged globals and thus drops the debug info for all of them.

This patch is enabling the old behavior for all MachO targets while
leaving all other targets unaffected.

rdar://problem/29160481
https://reviews.llvm.org/D26531

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286607 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 17:50:09 +00:00
Nemanja Ivanovic
3726719543 [PowerPC] Add vector conversion builtins to altivec.h - LLVM portion
This patch corresponds to review:
https://reviews.llvm.org/D26307

Adds all the intrinsics used for various conversion builtins that will
be added to altivec.h. These are type conversions between various types of
vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286596 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 14:41:19 +00:00
John Brawn
00180413cf Fix test/tools/gold/X86/thinlto_funcimport.ll on non-X86 hosts
Pass -m elf_x86_64 to gold, as is done in other tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286593 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 14:12:15 +00:00
Chad Rosier
0906927bc7 [AArch64] Enable merging of adjacent zero stores for all subtargets.
This optimization merges adjacent zero stores into a wider store.

e.g.,

strh wzr, [x0]
strh wzr, [x0, #2]
; becomes
str wzr, [x0]

e.g.,

str wzr, [x0]
str wzr, [x0, #4]
; becomes
str xzr, [x0]

Previously, this was only enabled for Kryo and Cortex-A57.

Differential Revision: https://reviews.llvm.org/D26396

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286592 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 14:10:12 +00:00
Ulrich Weigand
93f9010c1f [SystemZ] Support CL(G)T instructions
This adds support for the compare logical and trap (memory)
instructions that were added as part of the miscellaneous
instruction extensions feature with zEC12.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286587 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 12:48:26 +00:00
Ulrich Weigand
864946f0ea [SystemZ] Support load-and-zero-rightmost-byte facility
This adds support for the LZRF/LZRG/LLZRGF instructions that were
added on z13, and uses them for code generation were appropriate.

SystemZDAGToDAGISel::tryRISBGZero is updated again to prefer LLZRGF
over RISBG where both would be possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286586 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 12:46:28 +00:00
Ulrich Weigand
90353577ef [SystemZ] Use LLGT(R) instructions
This adds support for the 31-to-64-bit zero extension instructions
LLGT and LLGTR and uses them for code generation where appropriate.

Since this operation can also be performed via RISBG, we have to
update SystemZDAGToDAGISel::tryRISBGZero so that we prefer LLGT
over RISBG in case both are possible.  The patch includes some
simplification to the tryRISBGZero code; this is not intended
to cause any (further) functional change in codegen.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286585 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 12:43:51 +00:00
Simon Pilgrim
aa9211b5c6 [SelectionDAG] Add support for vector demandedelts in BSWAP opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286582 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 11:51:29 +00:00
Simon Pilgrim
970d6e800d [X86] Add knownbits vector BSWAP test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286579 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 11:33:21 +00:00
Simon Pilgrim
912c7ec127 [SelectionDAG] Add support for vector demandedelts in UREM/SREM opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286578 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 11:23:43 +00:00
Simon Pilgrim
afe6870832 [X86] Add knownbits vector UREM/SREM tests
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286577 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 11:11:40 +00:00
Simon Pilgrim
5809b919f1 [SelectionDAG] Add support for vector demandedelts in UDIV opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286576 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 10:47:24 +00:00
Simon Pilgrim
a597cc62da [X86] Add knownbits vector UDIV test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286575 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 10:39:15 +00:00
Diana Picus
286599a8f9 [ARM] Add plumbing for GlobalISel
Add GlobalISel skeleton, up to the point where we can select a ret void.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286573 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 08:27:37 +00:00
Matthias Braun
ee5205bfae ScheduleDAGInstrs: Add condjump deps to addSchedBarrierDeps()
addSchedBarrierDeps() is supposed to add use operands to the ExitSU
node. The current implementation adds uses for calls/barrier instruction
and the MBB live-outs in all other cases. The use
operands of conditional jump instructions were missed.

Also added code to macrofusion to set the latencies between nodes to
zero to avoid problems with the fusing nodes lingering around in the
pending list now.

Differential Revision: https://reviews.llvm.org/D25140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286544 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 01:34:21 +00:00
Stanislav Mekhanoshin
a0c045c407 Revert "[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies"
This reverts commit r286171, it breaks piglit test fs-discard-exit-2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286530 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 00:22:34 +00:00
Matthias Braun
773603e851 ScheduleDAGInstrs: Ignore dependencies of constant physregs
There is no need to track dependencies for constant physregs, as they
don't change their value no matter in what order you read/write to them.

Differential Revision: https://reviews.llvm.org/D26221

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286526 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 23:46:44 +00:00
Simon Pilgrim
c5bdc92c0d [SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286516 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:41:49 +00:00
Justin Lebar
a145558c9a [LSR] Tweak loop-strength-reduce-crash test. Test-only change.
Run opt instead of llc, and update the comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286515 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:37:13 +00:00
Peter Collingbourne
ca668e1942 IR: Introduce inrange attribute on getelementptr indices.
If the inrange keyword is present before any index, loading from or
storing to any pointer derived from the getelementptr has undefined
behavior if the load or store would access memory outside of the bounds of
the element selected by the index marked as inrange.

This can be used, e.g. for alias analysis or to split globals at element
boundaries where beneficial.

As previously proposed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-July/102472.html

Differential Revision: https://reviews.llvm.org/D22793

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286514 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:34:55 +00:00
Simon Pilgrim
d31cbc45ab [X86] Updated knownbits vector ADD/SUB test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286513 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:34:12 +00:00
Simon Pilgrim
d3f442dd4d [X86] Add knownbits vector ADD test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286511 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:21:04 +00:00
Simon Pilgrim
7a98835990 [SelectionDAG] Add support for splatted vectors in SUB opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286509 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:57:42 +00:00
Simon Pilgrim
d2d5b99bae [X86] Add knownbits vector SUB test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286508 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:50:23 +00:00
Matthias Braun
2821987cf3 RegisterCoalescer: Ignore interferences for constant physregs
When copying to/from a constant register interferences can be ignored.

Also update the documentation for isConstantPhysReg() to make it more
obvious that this transformation is valid.

Differential Revision: https://reviews.llvm.org/D26106

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286503 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:22:47 +00:00
Yaxun Liu
a2ee7d2991 AMDGPU: Emit runtime metadata as a note element in .note section
Currently runtime metadata is emitted as an ELF section with name .AMDGPU.runtime_metadata.

However there is a standard way to convey vendor specific information about how to run an ELF binary, which is called vendor-specific note element (http://www.netbsd.org/docs/kernel/elf-notes.html).

This patch lets AMDGPU backend emits runtime metadata as a note element in .note section.

Differential Revision: https://reviews.llvm.org/D25781


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286502 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:18:49 +00:00
Adam Nemet
9bf32e200d [OptDiag] Remove non-printable chars from function name
The r283656 did this in the remark arguments.  We also need to do this
in the main function attribute as that is written to YAML as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286482 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:47:03 +00:00
Simon Pilgrim
9ae088bf72 [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286481 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:43:52 +00:00
Simon Pilgrim
68c986108b [X86] Add knownbits vector TRUNC test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286477 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:24:33 +00:00
Teresa Johnson
62e70770b5 Restore part of "[ThinLTO] Prevent exporting of locals used/defined in module level asm"
This restores the part of r286297 that didn't require adding a
dependency from the Analysis to Object library. There are two parts
to the original fix, and this will address the handling for the case
where locals are used in module level asm.

The part that requires functionality in libObject handles local defs
in module level asm, and was reverted because our downstream build
of clang builds lib/Bitcode into a single library, and this new
dependency introduced a cycle there. I am trying to get that fixed
(see D26502), so for now that change isn't being restored

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286475 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:57:32 +00:00
Simon Pilgrim
e84f684084 [SelectionDAG] Add support for vector demandedelts in MUL opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286471 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:27:42 +00:00
Asaf Badouh
1d957ffe5a reproducer for pr29002
https://reviews.llvm.org/D26449

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286470 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:27:27 +00:00
Tom Stellard
0deee390af AMDGPU: Add VI i16 support
Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286464 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:02:37 +00:00
Simon Pilgrim
3cc5ea94f2 [X86] Add knownbits vector MUL test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286463 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 15:57:33 +00:00
Simon Pilgrim
2eb0b40c6a [SelectionDAG] Add support for vector demandedelts in SRA opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286461 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 15:05:09 +00:00
Sanjay Patel
80dc268da9 [InstCombine] auto-generate better checks; NFC
Note that the existing metadata checking was re-added by hand because the 
script doesn't currently know how to generate checks for lines outside of 
functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286460 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:58:17 +00:00
Simon Pilgrim
dbb1fda971 [X86] Add knownbits vector arithmetic shift test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286457 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:46:24 +00:00
Simon Pilgrim
0c5b3f0761 [DAGCombiner] Correctly extract the ConstOrConstSplat shift value for SHL nodes
We were failing to extract a constant splat shift value if the shifted value was being masked.

The (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV) combine was unnecessarily preventing this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286454 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:35:09 +00:00
Chad Rosier
1f5dcd896f Remove unnecessary check prefix directives. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286453 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:28:44 +00:00
Simon Pilgrim
3cc160451c [DAGCombiner] Show missed opportunity to UNDEF out-of-range SHL
Fails to match constant shift value due to presence of AND mask.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286452 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:19:45 +00:00
Tobias Grosser
541a4fd75d [RegionInfo] Add three tests that include infinite loops
These examples are variations that were inspired from a small subgraph taken
from paper.ll which are interesting as they show certain issues with infinite
loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286450 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:56:19 +00:00
Simon Pilgrim
f524b350db [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286448 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:52:42 +00:00
Simon Pilgrim
6392d731a4 [X86] Add knownbits vector logical shift test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286447 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:34:17 +00:00
Oliver Stannard
4a04eb017b [ARM] Thumb2 LDR (literal) should accept PC as the destination
The version of this instruction with the .w suffix already correctly accepts
this, but the alias without the .w did not.

Differential Revision: https://reviews.llvm.org/D26499



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286446 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:20:41 +00:00
Craig Topper
79013e50a6 [AVX-512] Allow legacy cvtpd2dq intrinsics to select EVEX encoded instruction when available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286435 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 07:47:17 +00:00