These functions are about classifying a global which will actually be
emitted, so it does not make sense for them to take a GlobalValue which may
for example be an alias.
Change the Mach-O object writer and the Hexagon, Lanai and MIPS backends to
look through aliases before using TargetLoweringObjectFile interfaces. These
are functional changes but all appear to be bug fixes.
Differential Revision: https://reviews.llvm.org/D25917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285006 91177308-0d34-0410-b5e6-96231b3b80d8
This adds a super basic implementation of a machine code disassembler.
It doesn't support any operands with custom encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284930 91177308-0d34-0410-b5e6-96231b3b80d8
Once MULHS was expanded, this exposed an issue where the condition
register was thought to be 16-bit. This caused an attempt to copy a
16-bit register to an 8-bit register.
Authored by Jake Goulding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283634 91177308-0d34-0410-b5e6-96231b3b80d8
We have a subtarget feature which we were ignoring, which was causing us
to generate unsupported instructions for some older chips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283317 91177308-0d34-0410-b5e6-96231b3b80d8
No tests are included just yet - this is used from the pseudo
instruction expander pass, which hasn't been pulled in-tree yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283316 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
This change adds the AVR assembly instruction printer.
No tests are included in this patch. I have left them downstream so we can
add them once `llc` successfully runs (there's very few components left
to upstream until this).
Reviewers: arsenm, kparzysz
Subscribers: wdng, beanz, mgorny
Differential Revision: https://reviews.llvm.org/D25028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282854 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
This adds the AVRMCTargetDesc file in tree. It allows creation of the
core classes used in the backend.
Reviewers: arsenm, kparzysz
Subscribers: wdng, beanz, mgorny
Differential Revision: https://reviews.llvm.org/D25023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282597 91177308-0d34-0410-b5e6-96231b3b80d8
We very recently landed the code. This commit enables the parser.
It also adds a missing include to AVRAsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282593 91177308-0d34-0410-b5e6-96231b3b80d8
The previous data layout caused issues when dealing with atomics.
Foe example, it is illegal to load a 16-bit value with less than 16-bits
of alignment.
This changes the data layout so that all types are aligned by at least
their own width.
Interestingly, this also _slightly_ decreased register pressure in some
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282587 91177308-0d34-0410-b5e6-96231b3b80d8
The main change is to return the code size from
InsertBranch/RemoveBranch.
Patch mostly by Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281505 91177308-0d34-0410-b5e6-96231b3b80d8
This is a mechanical change of comments in switches like fallthrough,
fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278902 91177308-0d34-0410-b5e6-96231b3b80d8
This is a mechanical change to make TargetLowering API take MachineInstr&
(instead of MachineInstr*), since the argument is expected to be a valid
MachineInstr. In one case, changed a parameter from MachineInstr* to
MachineBasicBlock::iterator, since it was used as an insertion point.
As a side effect, this removes a bunch of MachineInstr* to
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274287 91177308-0d34-0410-b5e6-96231b3b80d8
This is mostly a mechanical change to make TargetInstrInfo API take
MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator)
when the argument is expected to be a valid MachineInstr. This is a
general API improvement.
Although it would be possible to do this one function at a time, that
would demand a quadratic amount of churn since many of these functions
call each other. Instead I've done everything as a block and just
updated what was necessary.
This is mostly mechanical fixes: adding and removing `*` and `&`
operators. The only non-mechanical change is to split
ARMBaseInstrInfo::getOperandLatencyImpl out from
ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a
`MachineInstr*` which it updated to the instruction bundle leader; now,
the latter calls the former either with the same `MachineInstr&` or the
bundle leader.
As a side effect, this removes a bunch of MachineInstr* to
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.
Note: I updated WebAssembly, Lanai, and AVR (despite being
off-by-default) since it turned out to be easy. I couldn't run tests
for AVR since llc doesn't link with it turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274189 91177308-0d34-0410-b5e6-96231b3b80d8
