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37 Commits

Author SHA1 Message Date
Chuang-Yu Cheng
ff2190e04a [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance 
This patch implement the following instructions:
- addpcis subpcis
- maddhd maddhdu maddld
- modsw moduw modsd modud
- darn
- extswsli extswsli.
- setb
- dtstsfi dtstsfiq

Total 15 instructions

Reviewers: nemanjai hfinkel tjablin amehsan kbarton

http://reviews.llvm.org/D17885

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265505 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-04-06 01:47:02 +00:00
Chuang-Yu Cheng
c77546e444 [Power9] Implement copy-paste, msgsync, slb, and stop instructions 
This patch implements the following BookII and Book III instructions:
- copy copy_first cp_abort paste paste. paste_last
- msgsync
- slbieg slbsync
- stop

Total 10 instructions

Reviewers: nemanjai hfinkel tjablin amehsan kbarton

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265504 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-04-06 01:46:45 +00:00
Hal Finkel
184f8f7c10 [PowerPC] Enable printing instructions using aliases 
TableGen had been nicely generating code to print a number of instructions using
shorter aliases (and PowerPC has plenty of short mnemonics), but we were not
calling it. For some of the aliases we support in the parser, TableGen can't
infer the "inverse" alias relationship, so there is still more to do.

Thus, after some hours of updating test cases...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-23 18:30:38 +00:00
Hal Finkel
186abcb853 [PowerPC] Add asm support for cache-inhibited ld/st instructions 
Add assembler support for the fixed-point cache-inhibited load/store
instructions. These are hypervisor-level only, so don't get too excited ;)

Fixes PR21650.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222976 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-30 10:15:56 +00:00
Hal Finkel
b932ed3c3d [PowerPC] Add the 'attn' instruction 
The attn instruction is not part of the Power ISA, but is documented in the A2
user manual, and is accepted by the GNU assembler for the A2 and the POWER4+.
Reported as part of PR21650.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222712 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-25 00:30:11 +00:00
Joerg Sonnenberger
7ad7c75048 Add mfasr and mtasr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215110 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-07 13:35:34 +00:00
Joerg Sonnenberger
d94b6e8895 Add mfrtcu and mfrtcl instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215109 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-07 13:16:58 +00:00
Joerg Sonnenberger
80de56ebde Add RFID instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215105 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-07 12:39:59 +00:00
Joerg Sonnenberger
0f365741f3 Add lswi / stswi for assembler use with a warning to not add patterns 
for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214862 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-05 13:34:01 +00:00
Joerg Sonnenberger
977b978f93 Add features for PPC 4xx and e500/e500mc instructions. 
Move the test cases for them into separate files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214724 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-04 15:47:38 +00:00
Joerg Sonnenberger
a0e1d10f75 tlbia support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214640 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-02 20:16:29 +00:00
Joerg Sonnenberger
55f925abc5 mfdcr / mtdcr support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214639 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-02 20:00:26 +00:00
Joerg Sonnenberger
419f3804f0 Don't use additional arguments for dss and friends to satisfy DSS_Form, 
when let can do the same thing. Keep the 64bit variants as codegen-only.
While they have a different register class, the encoding is the same for
32bit and 64bit mode. Having both present would otherwise confuse the
disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214636 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-02 15:09:41 +00:00
Joerg Sonnenberger
cadb2a8a32 Add mtpid/mfpid for BookE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214363 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-30 23:59:11 +00:00
Joerg Sonnenberger
ee6a05091a Add rfdi and rfmci from the e500/e500mc ISA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214339 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-30 21:09:03 +00:00
Joerg Sonnenberger
a2d6cb1e55 SPRG 0 to 3 are valid outside BookE, so move them to the normal test 
file. Add support for accessing SPRG 4 to 7 on BookE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214295 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-30 09:24:37 +00:00
Joerg Sonnenberger
2f8f622d18 Fix typo in alias: DSIR -> DSISR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214238 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-29 22:42:44 +00:00
Joerg Sonnenberger
e31c7fd974 Add a number of aliases for SPR access. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214196 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-29 18:55:43 +00:00
Ulrich Weigand
47eac58333 [PowerPC] Generate little-endian object files 
As a first step towards real little-endian code generation, this patch
changes the PowerPC MC layer to actually generate little-endian object
files.  This involves passing the little-endian flag through the various
layers, including down to createELFObjectWriter so we actually get basic
little-endian ELF objects, emitting instructions in little-endian order,
and handling fixups and relocations as appropriate for little-endian.

The bulk of the patch is to update most test cases in test/MC/PowerPC
to verify both big- and little-endian encodings.  (The only test cases
*not* updated are those that create actual big-endian ABI code, like
the TLS tests.)

Note that while the object files are now little-endian, the generated
code itself is not yet updated, in particular, it still does not adhere
to the ELFv2 ABI.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204634 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-24 18:16:09 +00:00
Ulrich Weigand
3c99602ca8 [PowerPC] Add all trap mnemonics 
This adds support for all basic and extended variants
of the trap instructions to the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-04 14:40:12 +00:00
Ulrich Weigand
5606fcae50 [PowerPC] Add asm parser support for CR expressions 
This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-04 14:24:00 +00:00
Ulrich Weigand
33efedc048 [PowerPC] Use mtocrf when available 
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.

Current code however always emits mtcrf.  This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible.  It does create
inefficient code with the integrated assembler, however.

To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything.  Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.

As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-03 17:59:07 +00:00
Ulrich Weigand
44175d9715 [PowerPC] Support mtspr/mfspr in the asm parser 
This adds support for the generic forms of mtspr/mfspr
for the asm parser.  The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-03 12:32:41 +00:00
Ulrich Weigand
1307d8300f [PowerPC] Support all condition register logical instructions 
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-01 21:40:54 +00:00
Ulrich Weigand
1bc147c091 [PowerPC] Add extended rotate/shift mnemonics 
This adds all missing extended rotate/shift mnemonics to the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184834 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:17:41 +00:00
Ulrich Weigand
9c52f81e17 [PowerPC] Add extended subtract mnemonics 
This adds support for the extended subtract mnemonics to the asm parser:
   subi
   subis
   subic
   subic.
   sub
   sub.
   subc
   subc.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184832 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:16:48 +00:00
Ulrich Weigand
96fb3a25cb [PowerPC] Support some miscellaneous mnemonics in the asm parser 
This adds support for the following extended mnemonics:
  xnop
  mr.
  not
  not.
  la



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184767 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 18:08:03 +00:00
Ulrich Weigand
329d413199 [PowerPC] Add some FIXMEs 
A bunch of extendend mnemomics ought to support '.' forms.
Add FIXMEs to the test case for those.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184757 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 17:00:22 +00:00
Ulrich Weigand
2e8bd89503 [PowerPC] Add predicted forms of branches 
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
  For these, I've added new PPC::Predicate codes corresponding
  to the BO values for predicted branch forms, and updated insn
  printing to print them correctly.  I've also added new aliases
  for the asm parser matching the new forms.
- bt/bf
  I've added new aliases matching to gBC etc.
- bd(n)z variants
  I've added new instruction patterns for the predicted forms.

In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184754 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 16:52:04 +00:00
Ulrich Weigand
48473a8de5 [PowerPC] Add t/f branch mnemonics to asm parser 
This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the
asm parser, resolving to the generic conditional patterns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184725 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 12:49:20 +00:00
Ulrich Weigand
9679c47a07 [PowerPC] Support absolute branches 
There is currently only limited support for the "absolute" variants
of branch instructions.  This patch adds support for the absolute
variants of all branches that are currently otherwise supported.

This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.

While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.

No change in code generation intended.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184721 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 11:03:33 +00:00
Ulrich Weigand
9068d5310c [PowerPC] Support bd(n)zl and bd(n)zlrl 
This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184720 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 11:02:38 +00:00
Ulrich Weigand
813942a0cf [PowerPC] Support b(cond)l in the asm parser 
This patch adds support for the conditional variants of bl.
The pattern is currently used by the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184719 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 11:02:19 +00:00
Ulrich Weigand
7e66f5c1b4 [PowerPC] Support blrl and variants in the asm parser 
This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184718 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 11:01:55 +00:00
Ulrich Weigand
0db5379fe6 [PowerPC] Support compare mnemonics with implied CR0 
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).

This patch adds support for those extended compare mnemonics.


Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
 
 # CHECK: cmpdi 2, 3, 128                 # encoding: [0x2d,0x23,0x00,0x80]
          cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128                 # encoding: [0x2c,0x23,0x00,0x80]
+         cmpdi 3, 128
 # CHECK: cmpd 2, 3, 4                    # encoding: [0x7d,0x23,0x20,0x00]
          cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4                    # encoding: [0x7c,0x23,0x20,0x00]
+         cmpd 3, 4
 # CHECK: cmpldi 2, 3, 128                # encoding: [0x29,0x23,0x00,0x80]
          cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128                # encoding: [0x28,0x23,0x00,0x80]
+         cmpldi 3, 128
 # CHECK: cmpld 2, 3, 4                   # encoding: [0x7d,0x23,0x20,0x40]
          cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4                   # encoding: [0x7c,0x23,0x20,0x40]
+         cmpld 3, 4
 
 # CHECK: cmpwi 2, 3, 128                 # encoding: [0x2d,0x03,0x00,0x80]
          cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128                 # encoding: [0x2c,0x03,0x00,0x80]
+         cmpwi 3, 128
 # CHECK: cmpw 2, 3, 4                    # encoding: [0x7d,0x03,0x20,0x00]
          cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4                    # encoding: [0x7c,0x03,0x20,0x00]
+         cmpw 3, 4
 # CHECK: cmplwi 2, 3, 128                # encoding: [0x29,0x03,0x00,0x80]
          cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128                # encoding: [0x28,0x03,0x00,0x80]
+         cmplwi 3, 128
 # CHECK: cmplw 2, 3, 4                   # encoding: [0x7d,0x03,0x20,0x40]
          cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4                   # encoding: [0x7c,0x03,0x20,0x40]
+         cmplw 3, 4
 
 # FIXME: Trap mnemonics
 
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
 defm : BranchExtendedMnemonic<"nu", 100>;
 defm : BranchExtendedMnemonic<"ns", 100>;
 
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 16:15:12 +00:00
Ulrich Weigand
7c6f90d486 [PowerPC] Support branch mnemonics with implied CR0 
The extended branch mnemonics are supposed to use an implied CR0
if there is no explicit condition register specified.  This patch
adds extra variants of the mnemonics to this effect.

Problem reported by Joerg Sonnenberger.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183686 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-10 17:19:15 +00:00
Ulrich Weigand
16adfdb2e6 [PowerPC] Support extended mnemonics in AsmParser 
This patch adds infrastructure to support extended mnemonics in the
PowerPC assembler parser.  It adds support specifically for those
extended mnemonics that LLVM will itself generate.

The test case lists *all* extended mnemonics according to the
PowerPC ISA v2.06 Book I, but marks those not yet supported
as FIXME.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181051 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-03 19:50:27 +00:00