Commit Graph

111079 Commits

Author SHA1 Message Date
JF Bastien
544f63e84a Random Number Generator Refactoring (removing from Module)
This patch removes the RNG from Module. Passes should instead create a new RNG for their use as needed.

Patch by Stephen Crane @rinon.

Differential revision: http://reviews.llvm.org/D4377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224444 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 18:12:10 +00:00
Jingyue Wu
9830b459be [NVPTX] Fix bugs related to isSingleValueType
Summary:
With isSingleValueType starting to treat vector types as single-value types,
code that uses this interface needs to be updated.

Test Plan:
vector-global.ll
nvcl-param-align.ll

Reviewers: jholewinski

Reviewed By: jholewinski

Subscribers: llvm-commits, meheff, eliben, jholewinski

Differential Revision: http://reviews.llvm.org/D6573

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224440 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 17:59:04 +00:00
Timur Iskhodzhanov
898a22d7a5 Fix CR/LF line endings in test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 17:52:12 +00:00
Saleem Abdulrasool
de9e32a55d ARM: correct an off-by-one in an assert
The assert was off-by-one, resulting in failures for valid input.

Thanks to Asiri Rathnayake for pointing out the failure!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224432 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 16:17:44 +00:00
Michael Kuperstein
fd350586f5 [DAGCombine] Slightly improve lowering of BUILD_VECTOR into a shuffle.
This handles the case of a BUILD_VECTOR being constructed out of elements extracted from a vector twice the size of the result vector. Previously this was always scalarized. Now, we try to construct a shuffle node that feeds on extract_subvectors.

This fixes PR15872 and provides a partial fix for PR21711.

Differential Revision: http://reviews.llvm.org/D6678

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224429 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 12:32:17 +00:00
Vladimir Medic
73fb93cfaf MipsABIInfo class is used in different libraries. Moving the files to MCTargetDesc folder(LLVMMipsDesc library) prevents linkage errors. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 11:49:56 +00:00
Toma Tabacu
3fea427a63 [mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.
Summary:
When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives,
while GCC uses the default options if an assembly-level function contains inline assembly code.

This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example).

This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6637

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224425 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 10:56:16 +00:00
Suyog Sarda
4bfc4f2e8c Revert 224119 "This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling into vector of loads,
and vectorizes it." 

This was re-ordering floating point data types resulting in mismatch in output.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224424 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 10:34:27 +00:00
Yaron Keren
c0bd970d0e Teach lit.cfg to recognize -windows-gnu in addition to -mingw32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224421 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 09:55:15 +00:00
Elena Demikhovsky
982a8b3aeb Added 5 more tests related to sink store revision 224247
- by Ella Bolshinsky

http://reviews.llvm.org/D6420



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 08:12:59 +00:00
Erik Eckstein
96bd465d6c Strength reduce intrinsics with overflow into regular arithmetic operations if possible.
Some intrinsics, like s/uadd.with.overflow and umul.with.overflow, are already strength reduced.
This change adds other arithmetic intrinsics: s/usub.with.overflow, smul.with.overflow.
It completes the work on PR20194.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224417 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 07:29:19 +00:00
Duncan P. N. Exon Smith
80c5783c88 Revert "Linker: Drop superseded subprograms"
This reverts commit r224389.  Based on feedback from the bots, the
assertion seems to be going off *more* often, not less (previously I was
just seeing it in an internal bootstrap, now it's happening in public
builds too).

http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto_build/936/
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/5325

Reverting in order to investigate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224416 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 07:27:31 +00:00
Justin Hibbits
5fa882a5b7 Add parsing of 'foo@local".
Summary:
Currently, it supports generating, but not parsing, this expression.
Test added as well.

Test Plan: New test added, no regressions due to this.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6672

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224415 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 06:23:35 +00:00
Rafael Espindola
650708838d Remove a debugging assert.
Sorry for the noise, I have no idea how it survived to the final version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224414 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 03:38:04 +00:00
Rafael Espindola
5128bc1e74 Remove unused includes and out of date comment. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224413 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 03:07:20 +00:00
Rafael Espindola
9a845bdcd5 Fix the windows build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224412 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 02:42:20 +00:00
Rafael Espindola
2f569017cb Refactor and simplify the code reading /proc/cpuinfo. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224410 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 02:32:44 +00:00
Matthias Braun
b0de67232f RegisterCoalescer: Sprinkle some const modifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224409 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 02:18:13 +00:00
Duncan P. N. Exon Smith
c524b882e4 llvm-lto: Add testing coverage for local contexts
Add coverage in `llvm-lto` for the API exposed by libLTO to create
modules in local contexts.

The goal here isn't to test the symbol-related API extensively, just to
confirm that these modules work at all.  (I'll be shifting code around
soon that should be NFC and I realized there was no test coverage.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224408 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 02:00:38 +00:00
Nick Lewycky
7ecec5b0d4 Delete debugging cruft that crept in with r223802.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224407 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 01:56:51 +00:00
David Majnemer
891ec6d69f InstSimplify: shl nsw/nuw undef, %V -> undef
We can always choose an value for undef which might cause %V to shift
out an important bit except for one case, when %V is zero.

However, shl behaves like an identity function when the right hand side
is zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224405 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 01:54:33 +00:00
Nick Lewycky
9451a382ed Make ValueEnumerator::print use OS for metadata too. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224404 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 01:52:08 +00:00
Quentin Colombet
1e2604dccc [CodeGenPrepare] Reapply r224351 with a fix for the assertion failure:
The type promotion helper does not support vector type, so when make
such it does not kick in in such cases.

Original commit message:
[CodeGenPrepare] Move sign/zero extensions near loads using type promotion.

This patch extends the optimization in CodeGenPrepare that moves a sign/zero
extension near a load when the target can combine them. The optimization may
promote any operations between the extension and the load to make that possible.

Although this optimization may be beneficial for all targets, in particular
AArch64, this is enabled for X86 only as I have not benchmarked it for other
targets yet.


** Context **

Most targets feature extended loads, i.e., loads that perform a zero or sign
extension for free. In that context it is interesting to expose such pattern in
CodeGenPrepare so that the instruction selection pass can form such loads.
Sometimes, this pattern is blocked because of instructions between the load and
the extension. When those instructions are promotable to the extended type, we
can expose this pattern.


** Motivating Example **

Let us consider an example:
define void @foo(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
  %ld = load i8* %addr1
  %zextld = zext i8 %ld to i32
  %ld2 = load i32* %addr2
  %add = add nsw i32 %ld2, %zextld
  %sextadd = sext i32 %add to i64
  %zexta = zext i8 %a to i32
  %addza = add nsw i32 %zexta, %zextld
  %sextaddza = sext i32 %addza to i64
  %addb = add nsw i32 %b, %zextld
  %sextaddb = sext i32 %addb to i64
  call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
  ret void
}

As it is, this IR generates the following assembly on x86_64:
[...]
  movzbl  (%rdi), %eax   # zero-extended load
  movl  (%rsi), %es      # plain load
  addl  %eax, %esi       # 32-bit add
  movslq  %esi, %rdi     # sign extend the result of add
  movzbl  %dl, %edx      # zero extend the first argument
  addl  %eax, %edx       # 32-bit add
  movslq  %edx, %rsi     # sign extend the result of add
  addl  %eax, %ecx       # 32-bit add
  movslq  %ecx, %rdx     # sign extend the result of add
[...]
The throughput of this sequence is 7.45 cycles on Ivy Bridge according to IACA.

Now, by promoting the additions to form more extended loads we would generate:
[...]
  movzbl  (%rdi), %eax   # zero-extended load
  movslq  (%rsi), %rdi   # sign-extended load
  addq  %rax, %rdi       # 64-bit add
  movzbl  %dl, %esi      # zero extend the first argument
  addq  %rax, %rsi       # 64-bit add
  movslq  %ecx, %rdx     # sign extend the second argument
  addq  %rax, %rdx       # 64-bit add
[...]
The throughput of this sequence is 6.15 cycles on Ivy Bridge according to IACA.

This kind of sequences happen a lot on code using 32-bit indexes on 64-bit
architectures.

Note: The throughput numbers are similar on Sandy Bridge and Haswell.


** Proposed Solution **

To avoid the penalty of all these sign/zero extensions, we merge them in the
loads at the beginning of the chain of computation by promoting all the chain of
computation on the extended type. The promotion is done if and only if we do not
introduce new extensions, i.e., if we do not degrade the code quality.
To achieve this, we extend the existing “move ext to load” optimization with the
promotion mechanism introduced to match larger patterns for addressing mode
(r200947).
The idea of this extension is to perform the following transformation:
ext(promotableInst1(...(promotableInstN(load))))
=>
promotedInst1(...(promotedInstN(ext(load))))

The promotion mechanism in that optimization is enabled by a new TargetLowering
switch, which is off by default. In other words, by default, the optimization
performs the “move ext to load” optimization as it was before this patch.


** Performance **

Configuration: x86_64: Ivy Bridge fixed at 2900MHz running OS X 10.10.
Tested Optimization Levels: O3/Os
Tests: llvm-testsuite + externals.
Results:
- No regression beside noise.
- Improvements:
CINT2006/473.astar:  ~2%
Benchmarks/PAQ8p: ~2%
Misc/perlin: ~3%

The results are consistent for both O3 and Os.

<rdar://problem/18310086>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224402 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 01:36:17 +00:00
Kevin Enderby
e479df2161 Add printing the LC_ENCRYPTION_INFO_64 load command with llvm-objdump’s -private-headers
and add tests for the two AArch64 binaries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224400 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 01:01:30 +00:00
David Blaikie
7c3af9120c PR21875: codegen for non-type template parameters of nullptr_t type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224399 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 00:43:22 +00:00
Reid Kleckner
0c7f4e46b6 Revert "[CodeGenPrepare] Move sign/zero extensions near loads using type promotion."
This reverts commit r224351. It causes assertion failures when building
ICU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224397 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 00:29:23 +00:00
Hans Wennborg
74b5b195fd SelectionDAG switch lowering: use 'unsigned' to count destination popularity
SwitchInst::getNumCases() returns unsinged, so using uint64_t to count cases
seems unnecessary.

Also fix a missing CHECK in the test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224393 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 23:41:59 +00:00
Colin LeMahieu
526a14a344 [Hexagon] Updating doubleword shift usages to new versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 23:36:15 +00:00
Kevin Enderby
46a81fde99 Add printing the LC_ENCRYPTION_INFO load command with llvm-objdump’s -private-headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224390 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 23:25:52 +00:00
Duncan P. N. Exon Smith
d4017d0489 Linker: Drop superseded subprograms
When a function gets replaced by `ModuleLinker`, drop superseded
subprograms.  This ensures that the "first" subprogram pointing at a
function is the same one that `!dbg` references point at.

This is a stop-gap fix for PR21910.  Notably, this fixes Release+Asserts
bootstraps that are currently asserting out in
`LexicalScopes::initialize()` due to the explicit instantiations in
`lib/IR/Dominators.cpp` eventually getting replaced by -argpromotion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224389 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 23:23:41 +00:00
Sanjay Patel
9ab434750a fix typo, add spaces; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224384 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 22:48:42 +00:00
Simon Pilgrim
2385e98928 [X86][SSE] Vector double -> float conversion memory folding (cvtpd2ps)
Added a missing memory folding relationship for the (V)CVTPD2PS instruction - we can safely fold these for stack reloads.

Differential Revision: http://reviews.llvm.org/D6663



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224383 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 22:30:10 +00:00
Rafael Espindola
e1bf514b2b Make the assert a bit stronger.
We should get no declarations in here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224382 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 22:29:43 +00:00
Colin LeMahieu
84201cb2bd [Hexagon] Removing old XTYPE/BIT instructions and replacing usages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224381 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 22:17:09 +00:00
Sanjay Patel
128b2c383c merge consecutive loads that are offset from a base address
SelectionDAG::isConsecutiveLoad() was not detecting consecutive loads
when the first load was offset from a base address. 

This patch recognizes that pattern and subtracts the offset before comparing
the second load to see if it is consecutive.

The codegen change in the new test case improves from:

vmovsd	32(%rdi), %xmm0
vmovsd	48(%rdi), %xmm1 
vmovhpd	56(%rdi), %xmm1, %xmm1
vmovhpd	40(%rdi), %xmm0, %xmm0
vinsertf128	$1, %xmm1, %ymm0, %ymm0

To:

vmovups	32(%rdi), %ymm0

An existing test case is also improved from:

vmovsd	(%rdi), %xmm0
vmovsd	16(%rdi), %xmm1
vmovsd	24(%rdi), %xmm2
vunpcklpd	%xmm2, %xmm0, %xmm0 ## xmm0 = xmm0[0],xmm2[0]
vmovhpd	8(%rdi), %xmm1, %xmm3

To:

vmovsd	(%rdi), %xmm0
vmovsd	16(%rdi), %xmm1
vmovhpd	24(%rdi), %xmm0, %xmm0
vmovhpd	8(%rdi), %xmm1, %xmm1

This patch fixes PR21771 ( http://llvm.org/bugs/show_bug.cgi?id=21771 ).

Differential Revision: http://reviews.llvm.org/D6642



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224379 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 21:57:18 +00:00
Kevin Enderby
5b7369ddf5 Fix a bug in llvm-objdump’s -private-headers for the LC_VERSION_MIN_IPHONEOS
load command not getting printed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224376 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 21:48:27 +00:00
Colin LeMahieu
504c77f9c8 [Hexagon] Adding tstbit/bitclr/bitset instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224374 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 21:28:58 +00:00
Kostya Serebryany
95aa8cab27 [sanitizer] prevent function call merging for sanitizer-coverage callbacks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224372 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 21:24:15 +00:00
Kevin Enderby
85d57120aa Fix another use of PRIx32 that should have been PRIx64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224368 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 21:00:25 +00:00
Colin LeMahieu
18f28b2de6 [Hexagon] Adding bit count and twiddling instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224367 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 20:57:56 +00:00
Colin LeMahieu
50b3134fb4 [Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Doubleword abs/neg/not. Interleave and deinterleave instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224365 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 20:40:23 +00:00
Frederic Riss
f3ab9b9e63 [dsymutil] Pass the verbosity flag down to the processing. NFC for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224361 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 20:22:11 +00:00
Frederic Riss
aabd6c1ce8 [dsymutil] Avoid calling getStringTableData() for each symbol. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224360 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 20:21:34 +00:00
JF Bastien
50b8835451 x86-32: PUSHF/POPF use/def EFLAGS
Summary: As a side-quest for D6629 jvoung pointed out that I should use -verify-machineinstrs and this found a bug in x86-32's handling of EFLAGS for PUSHF/POPF. This patch fixes the use/def, and adds -verify-machineinstrs to all x86 tests which contain 'EFLAGS'. One exception: this patch leaves inline-asm-fpstack.ll as-is because it fails -verify-machineinstrs in a way unrelated to EFLAGS. This patch also modifies cmpxchg-clobber-flags.ll along the lines of what D6629 already does by also testing i386.

Test Plan: ninja check

Reviewers: t.p.northover, jvoung

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6687

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224359 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 20:15:45 +00:00
Rafael Espindola
192487e379 Use CastInst::castIsValid to simplify the verifier.
Also delete a dead member variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224356 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 19:29:29 +00:00
Matt Arsenault
ec6fabb9d3 NVPTX: Remove duplicate of AsmPrinter::lowerConstant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224355 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 19:16:17 +00:00
Matt Arsenault
8b5b0f5ee5 Move lowerConstant to AsmPrinter
This was a static function before, and NVPTX duplicated it
because it wasn't exposed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224354 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 19:16:14 +00:00
Quentin Colombet
93b6e016b1 [CodeGenPrepare] Move sign/zero extensions near loads using type promotion.
This patch extends the optimization in CodeGenPrepare that moves a sign/zero
extension near a load when the target can combine them. The optimization may
promote any operations between the extension and the load to make that possible.

Although this optimization may be beneficial for all targets, in particular
AArch64, this is enabled for X86 only as I have not benchmarked it for other
targets yet.


** Context **

Most targets feature extended loads, i.e., loads that perform a zero or sign
extension for free. In that context it is interesting to expose such pattern in
CodeGenPrepare so that the instruction selection pass can form such loads.
Sometimes, this pattern is blocked because of instructions between the load and
the extension. When those instructions are promotable to the extended type, we
can expose this pattern.


** Motivating Example **

Let us consider an example:
define void @foo(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
  %ld = load i8* %addr1
  %zextld = zext i8 %ld to i32
  %ld2 = load i32* %addr2
  %add = add nsw i32 %ld2, %zextld
  %sextadd = sext i32 %add to i64
  %zexta = zext i8 %a to i32
  %addza = add nsw i32 %zexta, %zextld
  %sextaddza = sext i32 %addza to i64
  %addb = add nsw i32 %b, %zextld
  %sextaddb = sext i32 %addb to i64
  call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
  ret void
}

As it is, this IR generates the following assembly on x86_64:
[...]
  movzbl  (%rdi), %eax   # zero-extended load
  movl  (%rsi), %es      # plain load
  addl  %eax, %esi       # 32-bit add
  movslq  %esi, %rdi     # sign extend the result of add
  movzbl  %dl, %edx      # zero extend the first argument
  addl  %eax, %edx       # 32-bit add
  movslq  %edx, %rsi     # sign extend the result of add
  addl  %eax, %ecx       # 32-bit add
  movslq  %ecx, %rdx     # sign extend the result of add
[...]
The throughput of this sequence is 7.45 cycles on Ivy Bridge according to IACA.

Now, by promoting the additions to form more extended loads we would generate:
[...]
  movzbl  (%rdi), %eax   # zero-extended load
  movslq  (%rsi), %rdi   # sign-extended load
  addq  %rax, %rdi       # 64-bit add
  movzbl  %dl, %esi      # zero extend the first argument
  addq  %rax, %rsi       # 64-bit add
  movslq  %ecx, %rdx     # sign extend the second argument
  addq  %rax, %rdx       # 64-bit add
[...]
The throughput of this sequence is 6.15 cycles on Ivy Bridge according to IACA.

This kind of sequences happen a lot on code using 32-bit indexes on 64-bit
architectures.

Note: The throughput numbers are similar on Sandy Bridge and Haswell.


** Proposed Solution **

To avoid the penalty of all these sign/zero extensions, we merge them in the
loads at the beginning of the chain of computation by promoting all the chain of
computation on the extended type. The promotion is done if and only if we do not
introduce new extensions, i.e., if we do not degrade the code quality.
To achieve this, we extend the existing “move ext to load” optimization with the
promotion mechanism introduced to match larger patterns for addressing mode
(r200947).
The idea of this extension is to perform the following transformation:
ext(promotableInst1(...(promotableInstN(load))))
=>
promotedInst1(...(promotedInstN(ext(load))))

The promotion mechanism in that optimization is enabled by a new TargetLowering
switch, which is off by default. In other words, by default, the optimization
performs the “move ext to load” optimization as it was before this patch.


** Performance **

Configuration: x86_64: Ivy Bridge fixed at 2900MHz running OS X 10.10.
Tested Optimization Levels: O3/Os
Tests: llvm-testsuite + externals.
Results:
- No regression beside noise.
- Improvements:
CINT2006/473.astar:  ~2%
Benchmarks/PAQ8p: ~2%
Misc/perlin: ~3%

The results are consistent for both O3 and Os.

<rdar://problem/18310086>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224351 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 19:09:03 +00:00
Kevin Enderby
6e5ad1fc76 Fix the arm build bots for a test that was added. A printing routine was incorrectly using PRIx32
when it should have been using PRIx64 for the value that was passed as uint64_t .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224350 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 18:58:11 +00:00
Robert Khasanov
41100285aa [AVX512] Enable integer arithmetic lowering for AVX512BW/VL subsets.
Added lowering tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224349 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 18:24:07 +00:00