42961 Commits

Author SHA1 Message Date
Craig Topper
5686a0d2ba [AVX-512] Add more VPTERNLOG patterns to enable folding of broadcast loads that aren't in operand 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295634 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-20 02:47:42 +00:00
Craig Topper
ffea086747 [X86] Use memory form of shift right by 1 when the rotl immediate is one less than the operation size.
An earlier commit already did this for the register form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295626 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-20 00:37:23 +00:00
Craig Topper
db343e334d [X86] Add test cases showing missed opportunities to use rotate right by 1 instructions when operation reads/writes memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295625 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-20 00:37:20 +00:00
Daniel Jasper
7c861d9e37 s/REQUIRES: Asserts/REQUIRES: asserts/
Other than this, we consistently use lower case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295623 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 23:26:00 +00:00
Craig Topper
97295ca181 [AVX-512] Disable peephole optimizations on the VPTERNLOG commute test. Add new patterns to enable isel to fold the loads on it own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295616 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 21:32:15 +00:00
Simon Pilgrim
f8d4b524dd [X86][SSE] Use getTargetConstantBitsFromNode to find zeroable shuffle elements.
Replaces existing approach that could only search BUILD_VECTOR nodes.

Requires getTargetConstantBitsFromNode to discriminate cases with all/partial UNDEF bits in each element - this should also be useful when we get around to supporting getTargetShuffleMaskIndices with UNDEF elements. 

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295613 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 19:40:31 +00:00
Craig Topper
07a0236401 [AVX-512] Add patterns to recognize masked vpternlog when the passthrough operand is not operand 0.
This uses a SDNodeXForm to swizzle the appropriate immediate bits to allow this to be matched.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295612 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 19:36:58 +00:00
Craig Topper
1a9a1132e0 [AVX-512] Add test cases that show failure to select masked VPTERNLOG when a select is used to force the passthru operand to be not operand 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295611 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 19:36:54 +00:00
Simon Pilgrim
0c9c0d47aa [X86][SSE] Enable initial support for domain crossing at high shuffle combine depths.
As discussed on D27692, this permits another domain to be used to combine a shuffle at high depths.

We currently set the required depth at 4 or more combined shuffles, this is probably too high for most targets but is a good starting point and already helps avoid a number of costly variable shuffles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295608 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 17:19:38 +00:00
Craig Topper
9ca276657a [AVX-512] Add broadcast VPTERNLOG instructions to special case commuting switch.
The instructions are marked commutable, but without special handling we don't get the immediate correct.

While here also remove the masked memory forms that aren't commutable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295602 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 08:03:26 +00:00
Craig Topper
1f1330b623 [AVX-512] Add patterns to show missed opportunities for folding vpternlog with broadcast loads. Also demonstrates a bug in the commuting of broadcast vpternlog instructions when we are able to select them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295601 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 08:03:23 +00:00
Daniel Berlin
1ca7d1765a Re-add debugcounter.ll with Requires: Asserts so that it only triggers when asserts are on
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295598 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 06:45:02 +00:00
Daniel Berlin
87d7001dbd Which, in turn, causes build bots to fail that have it unexpectedly passing. So remove debugcounter.ll for now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295597 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 04:56:07 +00:00
Daniel Berlin
996ea533d7 XFAIL this test until we figure out what to do here, since it will fail if NDEBUG defined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295596 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 04:55:02 +00:00
Daniel Berlin
2287817fa9 Add a DebugCounter for PredicateInfo renaming, and an associated test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295594 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 04:29:01 +00:00
NAKAMURA Takumi
7cca07f9d6 llvm/test/CodeGen/AMDGPU/r600.alu-limits.ll should require +Asserts. This would run into infinite loop anyways with -Asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295591 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-19 02:31:06 +00:00
Daniel Berlin
072a5a0f52 NewGVN: Start making use of predicateinfo pass.
Summary: This begins using the predicateinfo pass in NewGVN.

Reviewers: davide

Subscribers: llvm-commits, Prazek

Differential Revision: https://reviews.llvm.org/D29682

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295583 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 23:06:50 +00:00
Daniel Berlin
33e17b4040 PredicateInfo: Clean up predicate info a little, using insertion
helpers, and fixing support for the renaming the comparison.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295581 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 23:06:38 +00:00
Sanjay Patel
2b341046dd [InstCombine] add nsw/nuw X, signbit --> or X, signbit
Changing to 'or' (rather than 'xor' when no wrapping flags are set)
allows icmp simplifies to happen as expected.

Differential Revision: https://reviews.llvm.org/D29729


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295574 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 22:20:09 +00:00
Sanjay Patel
132ef2be48 [InstSimplify] add nsw/nuw (xor X, signbit), signbit --> X
The change to InstCombine in:
https://reviews.llvm.org/D29729
...exposes this missing fold in InstSimplify, so adding this
first to avoid a regression.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295573 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 21:59:09 +00:00
Sanjay Patel
f7584cdc50 [InstSimplify] add tests for add nsw/nuw (xor X, signbit), signbit --> X; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295572 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 21:51:14 +00:00
Craig Topper
58ee25f913 Recommit "[X86] Remove XOP VPCMOV intrinsics and autoupgrade them to native IR."
Clang has now been fixed to not use these intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295571 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 21:50:58 +00:00
Sanjay Patel
33dd286521 [x86] remove stale comments from tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295569 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 21:07:37 +00:00
Sanjay Patel
4c507d5052 [x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1
This is the same transform that is current used for:
select Bool, 0, -1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295568 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 21:03:28 +00:00
Craig Topper
b3d03a9308 Revert "[X86] Remove XOP VPCMOV intrinsics and autoupgrade them to native IR."
This reverts r295564. I missed that clang was still using the intrinsics despite our half implemented autoupgrade support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295565 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 20:14:20 +00:00
Craig Topper
aa2f6f93a2 [X86] Remove XOP VPCMOV intrinsics and autoupgrade them to native IR.
It seems we were already upgrading 128-bit VPCMOV, but the intrinsic was still defined and being used in isel patterns. While I was here I also simplified the tablegen multiclasses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295564 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 19:51:25 +00:00
Matt Arsenault
4371ec2c18 AMDGPU: Fix disassembly of aperture registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295555 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 18:41:41 +00:00
Matt Arsenault
83c857cd3a AMDGPU: Merge initial gfx9 support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295554 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 18:29:53 +00:00
Sanjay Patel
d0fd4adddf [InstCombine] add tests for trunc(insertelement); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295553 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 18:27:04 +00:00
Sanjay Patel
de80e80f01 [InstCombine] update trunc(shuffle) tests to reflect IR reality; NFC
We're ok shrinking splats, but not shuffles in general.

See https://reviews.llvm.org/D30123 for discussion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295547 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 15:24:31 +00:00
Craig Topper
47cf6aadec [AVX-512] Remove 128/256-bit masked fp max/min intrinsics. Upgrade them to legacy unmasked intrinsics and select instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295543 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 07:07:50 +00:00
Jan Vesely
aa04f11f4a AMDGPU/R600: Assert on infinite loop in EmitClauseMarkers
Differential Revision: https://reviews.llvm.org/D29792

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295539 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 04:24:10 +00:00
Dehao Chen
1ae1089dec Increases full-unroll threshold.
Summary:
The default threshold for fully unroll is too conservative. This patch doubles the full-unroll threshold

This change will affect the following speccpu2006 benchmarks (performance numbers were collected from Intel Sandybridge):

Performance:

403	0.11%
433	0.51%
445	0.48%
447	3.50%
453	1.49%
464	0.75%

Code size:

403	0.56%
433	0.96%
445	2.16%
447	2.96%
453	0.94%
464	8.02%

The compiler time overhead is similar with code size.

Reviewers: davidxl, mkuper, mzolotukhin, hfinkel, chandlerc

Reviewed By: hfinkel, chandlerc

Subscribers: mehdi_amini, zzheng, efriedma, haicheng, hfinkel, llvm-commits

Differential Revision: https://reviews.llvm.org/D28368

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295538 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 03:46:51 +00:00
Davide Italiano
8faf95ff17 [IR/Verifier] Don't visit DISubprograms more than needed.
Before this patch we happened to visit twice, one when scanning
MDNodes and the other one while visiting the function. Remove
the explicit call to visitDISubprogram there, so we don't emit
the same error twice in case the verifier fail and we save some
time when running it.
Thanks to Justin Bogner for the report and Adrian for the quick
review!

PR: 31995

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295537 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 03:02:44 +00:00
Matthias Braun
045ad1b55f machine-region-info.mir: Slightly simplify test, -mtriple
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295520 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 00:48:43 +00:00
Matthias Braun
5e55477ae5 MachineRegionInfo: Fix pass initialization
- Adapt MachineBasicBlock::getName() to have the same behavior as the IR
  BasicBlock (Value::getName()).
- Add it to lib/CodeGen/CodeGen.cpp::initializeCodeGen so that it is linked in
  the CodeGen library.
- MachineRegionInfoPass's name conflicts with RegionInfoPass's name ("region").
- MachineRegionInfo should depend on MachineDominatorTree,
  MachinePostDominatorTree and MachineDominanceFrontier instead of their
  respective IR versions.
- Since there were no tests for this, add a X86 MIR test.

Patch by Francis Visoiu Mistrih<fvisoiumistrih@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295518 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 00:41:16 +00:00
Justin Bogner
a39b1ce61f Verifier: Disallow a line number without a file in DISubprogram
A line number doesn't make much sense if you don't say where it's
from. Add a verifier check for this and update some tests that had
bogus debug info.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295516 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 23:57:42 +00:00
Sanjay Patel
e581944506 [InstCombine] add tests for trunc(shuffle X, C, M); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295513 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 23:16:54 +00:00
Matthias Braun
92e3dc4c50 AArch64LoadStoreOptimizer: Correctly clear kill flags
When promoting the Load of a Store-Load pair to a COPY all kill flags
between the store and the load need to be cleared.

rdar://30402435

Differential Revision: https://reviews.llvm.org/D30110

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295512 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 23:15:03 +00:00
Simon Pilgrim
6bd44f2375 [X86] Add MOVBE targets to load combine tests
Test folded endian swap tests with MOVBE instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295508 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 23:00:21 +00:00
Guozhi Wei
4d5bc87951 [PPC] Give unaligned memory access lower cost on processor that supports it
Newer ppc supports unaligned memory access, it reduces the cost of unaligned memory access significantly. This patch handles this case in PPCTTIImpl::getMemoryOpCost.

This patch fixes pr31492.

Differential Revision: https://reviews.llvm.org/D28630

This is resubmit of r292680, which was reverted by r293092. The internal application failures were actually caused by a source code bug.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295506 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 22:29:39 +00:00
Krzysztof Parzyszek
eee70a1f65 [Hexagon] Start using regmasks on calls
Reapply r295371 with a fix for the Windows bot failures.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295504 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 22:14:51 +00:00
Simon Pilgrim
fcd878d181 [X86] Add subborrow stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295496 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 21:16:24 +00:00
Sanjay Patel
69382f1737 [x86] add tests for sext (not bool); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295495 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 21:10:40 +00:00
Simon Pilgrim
d1ecc080dc [X86][SSE] Add (V)MOVD folding pattern with zextloadi64i32 load node.
Fixes PRPR31309

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295492 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 20:43:32 +00:00
Adrian Prantl
75f00d80fb Fix windows bots by locking down the target triple on this testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295490 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 20:02:26 +00:00
Matt Arsenault
0f6af2352e AMDGPU: Fix crashes on invalid icmp/fcmp intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295489 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 19:49:10 +00:00
Peter Collingbourne
063d4cbbef WholeProgramDevirt: For VCP use a 32-bit ConstantInt for the byte offset.
A future change will cause this byte offset to be inttoptr'd and then exported
via an absolute symbol. On the importing end we will expect the symbol to be
in range [0,2^32) so that it will fit into a 32-bit relocation. The problem
is that on 64-bit architectures if the offset is negative it will not be in
the correct range once we inttoptr it.

This change causes us to use a 32-bit integer so that it can be inttoptr'd
(which zero extends) into the correct range.

Differential Revision: https://reviews.llvm.org/D30016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295487 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 19:43:45 +00:00
Adrian Prantl
7e8d980564 Debug Info: Sort frame index expressions before emitting them.
This fixes PR31381, which caused an assertion and/or invalid debug info.

This affects debug variables that have multiple fragments in the MMI
side (i.e.: in the stack frame) table.
rdar://problem/30571676

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295486 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 19:42:32 +00:00
Simon Pilgrim
b8890befb4 [X86][SHA] Add SHA stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295479 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17 19:24:55 +00:00