25003 Commits

Author SHA1 Message Date
Rafael Espindola
5c37d1622d Use ELFOSABI_NONE instead of ELFOSABI_LINUX.
The doesn't seem to be a difference and ELFOSABI_NONE seems to be far more
common:

* Linux doesn't care when loading and puts ELFOSABI_NONE on core dumps.
* Gold and bfd ld produce files with ELFOSABI_NONE.
* Gold and bfd ld seems to ignore EI_OSABI other than for freebsd.
* Gas puts ELFOSABI_NONE in most .o files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248534 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 20:57:24 +00:00
Matt Arsenault
d0edb1f758 AMDGPU: Add s_dcache_* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248533 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 19:52:27 +00:00
Matt Arsenault
1348e9d04d AMDGPU: Add cache invalidation instructions.
These are necessary for implementing mem_fence for
OpenCL 2.0.

The VI assembler tests are disabled since it seems to be
using the wrong encoding or opcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248532 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 19:52:21 +00:00
Sanjoy Das
5b674c0b49 [IR] Add operand bundles to CallInst and InvokeInst.
Summary:
This change teaches `CallInst`s and `InvokeInst`s to maintain a set of
operand bundles as part of its operands.  `CallInst`s and `InvokeInst`s
with operand bundles co-allocate some space before their `Use` array to
hold meta information about which of its operands are part of an operand
bundle.

The strings corresponding to the bundle tags are interned into
`LLVMContextImpl::BundleTagCache`

This change does not include any parsing / bitcode support.  That's the
next change.

Depends on D12455.

Reviewers: reames, chandlerc, majnemer, dexonsmith, kmod, JosephTremoulet, rnk, bogner

Subscribers: MatzeB, sanjoy, llvm-commits

Differential Revision: http://reviews.llvm.org/D12456

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248527 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 19:14:18 +00:00
Artyom Skrobov
c848236c93 [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a
hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with
a FIXME: attached.

This patch changes the handling of +t2dsp to be in line with other
architecture extensions.

Following a revert of r248152 and new review comments, this patch also includes
renaming FeatureDSPThumb2 -> FeatureDSP, hasThumb2DSP() -> hasDSP(), etc.
The spelling of "t2dsp" is preserved, pending a further investigation of its
possible external usage.

Differential Revision: http://reviews.llvm.org/D12937



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248519 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 17:31:16 +00:00
Matt Arsenault
b10121bd9d Introduce target hook for optimizing register copies
Allow a target to do something other than search for copies
that will avoid cross register bank copies.

Implement for SI by only rewriting the most basic copies,
so it should look through anything like a subregister extract.

I'm not entirely satisified with this because it seems like
eliminating a reg_sequence that isn't fully used should work
generically for all targets without them having to override
something. However, it seems to be tricky to have a simple
implementation of this without rewriting to invalid  kinds
of subregister copies on some targets.

I'm not sure if there is currently a generic way to easily check
if a subregister index would be valid for the current use.
The current set of TargetRegisterInfo::get*Class functions don't
quite behave like I would expect (e.g. getSubClassWithSubReg
returns the maximal register class rather than the minimal), so
I'm not sure how to make the generic test keep searching if
SrcRC:SrcSubReg is a valid replacement for DefRC:DefSubReg. Making
the default implementation to check for simple copies breaks
a variety of ARM and x86 tests by producing illegal subregister uses.

The ARM tests are not actually changed since it should still be using
the same sharesSameRegisterFile implementation, this just relaxes
them to not check for specific registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248478 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 08:36:14 +00:00
Justin Bogner
f790439073 BasicAA: Move BasicAAResult::alias out-of-line. NFC
This makes the header more readable and cleans up some unnecessary
header differences between NDEBUG and !NDEBUG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248462 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 04:59:24 +00:00
Sanjoy Das
4769a7486b [IR] Teach llvm::User to co-allocate a descriptor.
Summary:
With this change, subclasses of `llvm::User` will be able to co-allocate
a variable number of bytes (called a "descriptor") with the `llvm::User`
instance.  The co-allocated descriptor can later be accessed using
`llvm::User::getDescriptor`.  This will be used in later changes to
implement operand bundles.

This change steals one bit from `NumUserOperands`, but given that it is
still 28 bits wide I don't think this will be a practical issue.

This change does not allow allocating hung off uses with descriptors.
This only for simplicity, not for any fundamental reason; and we can
easily add this functionality later if needed.

Reviewers: reames, chandlerc, dexonsmith, kmod, majnemer, pete, JosephTremoulet

Subscribers: pete, sanjoy, llvm-commits

Differential Revision: http://reviews.llvm.org/D12455

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248453 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 01:00:49 +00:00
Rui Ueyama
e81b32f4f5 Remove iterator_range::end.
Because the current proposal does not include that member function,
and we are trying to keep in line with that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248451 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 00:23:07 +00:00
Rui Ueyama
d25f78f64a Add iterator_range::end() predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248447 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-23 23:58:29 +00:00
Sanjay Patel
dbd50cefa1 set div/rem default values to 'expensive' in TargetTransformInfo's cost model
...because that's what the cost model was intended to do.

As discussed in D12882, this fix has a temporary unintended consequence for
SimplifyCFG: it causes us to not speculate an fdiv. However, two wrongs make
PR24818 right, and two wrongs make PR24343 act right even though it's really
still wrong.

I intend to correct SimplifyCFG and add to CodeGenPrepare to account for this
cost model change and preserve the righteousness for the bug report cases.

https://llvm.org/bugs/show_bug.cgi?id=24818
https://llvm.org/bugs/show_bug.cgi?id=24343

Differential Revision: http://reviews.llvm.org/D12882



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248439 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-23 22:28:18 +00:00
Philip Reames
710fde8868 [docs] Update DominatorTree docs to clarify expectations around unreachable blocks
Note: I'm am not trying to describe what "should be"; I'm only describing what is true today.

This came out of my recent question to llvm-dev titled: When can the dominator tree not contain a node for a basic block?

Differential Revision: http://reviews.llvm.org/D13078



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248417 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-23 18:39:37 +00:00
Evgeniy Stepanov
d4052cf84c Android support for SafeStack.
Add two new ways of accessing the unsafe stack pointer:

* At a fixed offset from the thread TLS base. This is very similar to
  StackProtector cookies, but we plan to extend it to other backends
  (ARM in particular) soon. Bionic-side implementation here:
  https://android-review.googlesource.com/170988.
* Via a function call, as a fallback for platforms that provide
  neither a fixed TLS slot, nor a reasonable TLS implementation (i.e.
  not emutls).

This is a re-commit of a change in r248357 that was reverted in
r248358.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248405 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-23 18:07:56 +00:00
Sanjoy Das
6d6e2b5a35 [SCEV] Introduce ScalarEvolution::getOne and getZero.
Summary:
It is fairly common to call SE->getConstant(Ty, 0) or
SE->getConstant(Ty, 1); this change makes such uses a little bit
briefer.

I've refactored the call sites I could find easily to use getZero /
getOne.

Reviewers: hfinkel, majnemer, reames

Subscribers: sanjoy, llvm-commits

Differential Revision: http://reviews.llvm.org/D12947

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248362 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-23 01:59:04 +00:00
Evgeniy Stepanov
1be7ea773a Revert "Android support for SafeStack."
test/Transforms/SafeStack/abi.ll breaks when target is not supported;
needs refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248358 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-23 01:23:22 +00:00
Evgeniy Stepanov
c7b6dc0535 Android support for SafeStack.
Add two new ways of accessing the unsafe stack pointer:

* At a fixed offset from the thread TLS base. This is very similar to
  StackProtector cookies, but we plan to extend it to other backends
  (ARM in particular) soon. Bionic-side implementation here:
  https://android-review.googlesource.com/170988.
* Via a function call, as a fallback for platforms that provide
  neither a fixed TLS slot, nor a reasonable TLS implementation (i.e.
  not emutls).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248357 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-23 01:03:51 +00:00
Adrian Prantl
02aa134d92 IR: Add a setDWOId() method to DICompileUnit.
Tested via clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248342 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 23:21:06 +00:00
Adrian Prantl
c3ff2abcb0 IR: Fix the return value of DICompileUnit::getDWOId.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248341 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 23:21:03 +00:00
Aaron Ballman
9800f4ca6e Instead of defining the operator delete() function, it is better to delete the function so that any uses (even from within Node or its subclasses) do not accidentally call it. NFC intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248320 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 21:00:35 +00:00
Ahmed Bougacha
ee629d8395 [AArch64] Emit clrex in the expanded cmpxchg fail block.
In the comparison failure block of a cmpxchg expansion, the initial
ldrex/ldxr will not be followed by a matching strex/stxr.
On ARM/AArch64, this unnecessarily ties up the execution monitor,
which might have a negative performance impact on some uarchs.

Instead, release the monitor in the failure block.
The clrex instruction was designed for this: use it.

Also see ARMARM v8-A B2.10.2:
"Exclusive access instructions and Shareable memory locations".

Differential Revision: http://reviews.llvm.org/D13033

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248291 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 17:21:44 +00:00
NAKAMURA Takumi
ccf2ea372c Prune trailing whitespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248265 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 11:19:03 +00:00
NAKAMURA Takumi
c36e746e98 Reformat blank lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248263 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 11:14:39 +00:00
NAKAMURA Takumi
6902c8db26 Reformat comment lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248262 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 11:14:12 +00:00
NAKAMURA Takumi
d4cdf1962b Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248261 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 11:13:55 +00:00
Matthias Braun
95e05ddf74 LiveIntervalAnalysis: Factor common code into splitSeparateComponents; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248241 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 03:44:41 +00:00
Matthias Braun
66c643ef82 Remove declarations for methods that do not exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248238 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 01:52:44 +00:00
NAKAMURA Takumi
00a0a4bbad Fix r248164. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248237 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 01:44:21 +00:00
Stephen Canon
ff278be8cf Remove roundingMode argument in APFloat::mod
Because mod is always exact, this function should have never taken a rounding mode argument.  The actual implementation still has issues, which I'll look at resolving in a subsequent patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248195 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 19:29:25 +00:00
Chandler Carruth
56fa307e51 [ADT] Remove a couple of the always inline attributes I added.
Based on conversations with Justin and a few others, these constructors
are really useful to have in the executable so that you can call them
from the debugger. After some measurements, these *particular* calls
aren't so problematic as to make them a good tradeoff for always inline.

Please let me know if there are other functions really needed for
debugging. The always inline attribute is a hack that we should only
really employ when it doesn't hurt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248188 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 18:02:24 +00:00
Marcello Maggioni
eaf5bf9900 [DivergenceAnalysis] Separated definition of class into header.
The definition of the DivergenceAnalysis pass was in a CPP
file and wasn't accessible to users of the analysis to get it
through "getAnalysis<>()".
This patch extracts the definition into a separate header that
can be used by users of the analysis to fetch the results.

Patch by Volkan Keles (vkeles@apple.com)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248186 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 17:58:14 +00:00
James Molloy
7d3733cd0d Revert "[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def"
This was committed without the code review (http://reviews.llvm.org/D12937) being approved.

This reverts commit r248152.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248174 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 16:35:08 +00:00
Matt Arsenault
7c64ca7328 Fix missing C++ mode comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248167 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 15:59:41 +00:00
Chad Rosier
c5d4530d42 [Machine Combiner] Refactor machine reassociation code to be target-independent.
No functional change intended.
Patch by Haicheng Wu <haicheng@codeaurora.org>!

http://reviews.llvm.org/D12887
PR24522

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248164 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 15:09:11 +00:00
Artyom Skrobov
7dfb31c329 [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a
hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with
a FIXME: attached.

This patch changes the handling of +t2dsp to be in line with other
architecture extensions.

Following review comments, also updating the description of FeatureDSPThumb2
in ARM.td.

Differential Revision: http://reviews.llvm.org/D12937



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248152 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 12:43:10 +00:00
Craig Topper
795a06a046 Use makeArrayRef or None to avoid unnecessarily mentioning the ArrayRef type extra times. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248140 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 05:32:41 +00:00
Craig Topper
2e1b727d8d Don't pass StringRefs around by const reference. Pass by value instead per coding standards. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248136 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 00:18:00 +00:00
Craig Topper
634763c0f5 Cleanup places that passed SMLoc by const reference to pass it by value instead. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248135 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 23:35:59 +00:00
Igor Breger
b0eb8fb69c AVX512: Implemented encoding and intrinsics for vcmpss/sd.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248121 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 15:15:10 +00:00
Asaf Badouh
fe11ff1d50 [X86][AVX512] extend support in Scalar conversion
add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics

Differential Revision: http://reviews.llvm.org/D12665

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248117 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 14:31:19 +00:00
Igor Breger
0d48c46954 AVX512: vsqrtss/sd encoding and intrinsics implementation.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12102

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248116 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 09:13:41 +00:00
Asaf Badouh
d3db2cf572 [X86][AVX512DQ] Add fpclass instruction
Differential Revision: http://reviews.llvm.org/D12931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248115 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 08:46:07 +00:00
Igor Breger
d425988995 AVX512: Implemented intrinsics for vshuff32x4, vshuff64x2, vshufi64x2, vshufi32x4
Added tests for intrinsics.

Differential Revision: http://reviews.llvm.org/D12525

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248113 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 07:18:53 +00:00
Igor Breger
28cce2ad25 AVX512: Implement instructions encoding, lowering and intrinsics
vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.

Differential Revision: http://reviews.llvm.org/D11893

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248111 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 06:52:42 +00:00
Rafael Espindola
26a99b2dc8 This code never uses r_addend, so it can just use Elf_Rel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248040 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-18 21:12:38 +00:00
Davide Italiano
5310d9c491 [Object/ELF] Change comment to reflect reality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248032 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-18 20:41:15 +00:00
Teresa Johnson
c4736349a5 Remove couple of new Bitcode enum vals that snuck in via r247927 (NFC)
These are meant to be part of the follow on patch I am sending for
review shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248023 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-18 19:38:53 +00:00
Larisse Voufo
69328805da Clean up: Refactoring the hardcoded value of 6 for FindAvailableLoadedValue()'s parameter MaxInstsToScan. (Complete version of r247497. See D12886)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248022 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-18 19:14:35 +00:00
James Y Knight
dc18fbbb2d Make MachineScheduler debug output less confusing.
At least...a little bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248020 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-18 18:52:20 +00:00
Matthias Braun
6c76d11db8 SelectionDAG: Introduce PersistentID to SDNode for assert builds.
This gives us more human readable numbers to identify nodes in debug
dumps.

Before:
  0x7fcbd9700160: ch = EntryToken

  0x7fcbd985c7c8: i64 = Register %RAX

   ...

      0x7fcbd9700160: <multiple use>
    0x7fcbd985c578: i64,ch = MOV64rm 0x7fcbd985c6a0, 0x7fcbd985cc68, 0x7fcbd985c200, 0x7fcbd985cd90, 0x7fcbd985ceb8, 0x7fcbd9700160<Mem:LD8[@foo]> [ORD=2]

  0x7fcbd985c8f0: ch,glue = CopyToReg 0x7fcbd9700160, 0x7fcbd985c7c8, 0x7fcbd985c578 [ORD=3]

    0x7fcbd985c7c8: <multiple use>
    0x7fcbd985c8f0: <multiple use>
    0x7fcbd985c8f0: <multiple use>
  0x7fcbd985ca18: ch = RETQ 0x7fcbd985c7c8, 0x7fcbd985c8f0, 0x7fcbd985c8f0:1 [ORD=3]

Now:
  t0: ch = EntryToken

  t5: i64 = Register %RAX

    ...

      t0: <multiple use>
    t3: i64,ch = MOV64rm t10, t12, t11, t13, t14, t0<Mem:LD8[@foo]> [ORD=2]

  t6: ch,glue = CopyToReg t0, t5, t3 [ORD=3]

    t5: <multiple use>
    t6: <multiple use>
    t6: <multiple use>
  t7: ch = RETQ t5, t6, t6:1 [ORD=3]

Differential Revision: http://reviews.llvm.org/D12564

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248010 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-18 17:41:00 +00:00
Yaron Keren
81a5ddcd9f Simplify SmallBitVector::applyMask by consolidating common code for 32- and 64-bit builds
and assert when mask is too large to apply in the small case,
previously the extra words were silently ignored.
clang-format the entire function to match current code standards.

This is a rewrite of r247972 which was reverted in r247983 due to
warning and possible UB on 32-bits hosts.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247993 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-18 15:08:24 +00:00