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45 Commits

Author SHA1 Message Date
Richard Osborne
8f9c5cca4f Add Uses=[SP] to call instructions. This fixes a miscompilation with a 
variable sized alloca.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138433 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 13:32:43 +00:00
Richard Osborne
c4dcf323cc Add intrinsics for SETEV, GETED, GETET. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137938 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 13:00:48 +00:00
Richard Osborne
c8007ab582 Add intrinsics for the zext / sext instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135476 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 13:28:50 +00:00
Richard Osborne
829bef1a46 Add intrinsics for the testct, testwct instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135475 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 13:00:40 +00:00
Richard Osborne
dee3dd9129 Add intrinsics for the peek and endin instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135474 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 12:50:25 +00:00
Richard Osborne
a9b08aa25e Fix 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-31 16:30:33 +00:00
Richard Osborne
9497466190 Add XCore intrinsic for crc8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132340 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-31 16:24:49 +00:00
Richard Osborne
7736c37c14 Add XCore intrinsic for crc32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-31 14:47:36 +00:00
Richard Osborne
e8f3533323 Add XCore intrinsics for initializing / starting / synchronizing threads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128633 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 15:13:13 +00:00
Richard Osborne
11bd0784d9 Add XCore intrinsic for setpsc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127821 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-17 18:42:05 +00:00
Richard Osborne
e17139b3e9 Add XCore intrinsics for setclk, setrdy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127761 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-16 21:56:00 +00:00
Richard Osborne
bb057453db Add checkevent intrinsic to check if any resources owned by the current thread 
can event.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127741 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-16 18:34:00 +00:00
Richard Osborne
5aad8b3e78 Add XCore intrinsics for getps, setps, setsr and clrsr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127678 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-15 13:45:47 +00:00
Richard Osborne
21d7eb3f3b Add XCore intrinsic for eeu instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126384 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 13:39:18 +00:00
Richard Osborne
d04b4937d1 Add XCore intrinsic for clre instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 18:52:05 +00:00
Richard Osborne
9935bd0819 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 18:35:59 +00:00
Richard Osborne
292f62e06f Add XCore intrinsic for the setv instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 16:46:37 +00:00
Richard Osborne
2254d0eaa1 Fix format for setc instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126314 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 15:20:16 +00:00
Richard Osborne
2a2cb28526 Add XCore intrinsic for settw instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 14:45:03 +00:00
Richard Osborne
d83318450b Add XCore intrinsics for various instructions on ports. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126132 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-21 18:23:30 +00:00
Richard Osborne
59982f3ffc Add intrinsic for setc instruction on the XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125186 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-09 13:22:12 +00:00
Richard Osborne
17c1e51d22 Add XCore intrinsics for resource instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-03 13:14:25 +00:00
Chris Lattner
036609bd7d Flag -> Glue, the ongoing saga 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-23 18:28:41 +00:00
Jakob Stoklund Olesen
7853cd0bea Remove Predicate_* calls from MBlaze and XCore 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112920 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-03 00:35:16 +00:00
Eric Christopher
4a232f0836 Remove isTwoAddress from XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106446 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:51:38 +00:00
Chris Lattner
263bd9abe2 fix a type contradition: XCoreISD::RETSP has one argument, not zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-28 08:47:39 +00:00
Chris Lattner
60e9eac357 set SDNPVariadic on nodes throughout the rest of the targets that 
need them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 05:33:51 +00:00
Richard Osborne
8acf71baed Don't mark call instruction as a barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96983 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-23 21:08:11 +00:00
Richard Osborne
3abd8d4e03 ECALLF, ECALLT shouldn't be marked as barriers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-23 18:29:49 +00:00
Richard Osborne
4ee2aa7eb2 Mark unconditional branches as barriers. Found using -verify-machineinstrs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96960 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-23 18:13:38 +00:00
Richard Osborne
78700b0c55 Lower BR_JT on the XCore to a jump into a series of jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-23 13:25:07 +00:00
Dan Gohman
f451cb870e Fix "the the" and similar typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-10 16:03:48 +00:00
Richard Osborne
bea7df56ce Add XCore support for indirectbr / blockaddress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89273 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-18 23:20:42 +00:00
Dan Gohman
adaace8aa8 Set isBarrier = 1 on return instructions, as they are control barriers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86851 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-11 18:11:07 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Richard Osborne
c96c8e0e81 Add some peepholes for signed comparisons using ashr X, X, 32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83549 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 15:38:17 +00:00
Richard Osborne
f9416ea0cd Remove xs1b predicate since it is no longer needed to differentiate betweem 
xs1a and xs1b.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83383 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 16:17:57 +00:00
Richard Osborne
34bee6da7a Remove xs1a subtarget. xs1a is a preproduction device used in 
early development boards which is no longer supported in the
XMOS toolchain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 16:01:09 +00:00
Richard Osborne
d558ea5e0a Add extra SEXT pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77920 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 22:45:24 +00:00
Richard Osborne
1d05b237a5 Fix pattern for LD16S_3r, add basic tests to check load / store instructions 
are being properly selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75797 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 17:06:59 +00:00
Bill Wendling
51b16f4737 Untabification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-30 01:09:53 +00:00
Richard Osborne
29cab5f0ee Add pseudo instructions to the XCore for (load|store|load address) of a 
frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.

This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62238 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-14 18:26:46 +00:00
Richard Osborne
269bc0042f Add support for ISD::TRAP to the XCore backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60479 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-03 10:59:16 +00:00
Richard Osborne
1d8f975890 Add XCore intrinsics for getid (returns thread id) and bitrev (reverses 
bits in a word).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59296 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-14 10:12:16 +00:00
Richard Osborne
b25baef26f Add XCore backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58838 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-07 10:59:00 +00:00