128725 Commits

Author SHA1 Message Date
Nikolay Haustov
63cffd62c1 [AMDGPU] Assembler: change v_madmk operands to have same order as mad.
The constant is now at source operand 1 (previously at 2).
This is also how it is in legacy AMD sp3 assembler.
Update tests.

Differential Revision: http://reviews.llvm.org/D17984

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263212 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 09:27:25 +00:00
Chandler Carruth
f51faf0abd [PM/AA] Teach the AAManager how to handle module analyses in addition to
function analyses, and use it to wire up globals-aa to the new pass
manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263211 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 09:15:11 +00:00
Chandler Carruth
dd15ed0335 [PM] Port GVN to the new pass manager, wire it up, and teach a couple of
tests to run GVN in both modes.

This is mostly the boring refactoring just like SROA and other complex
transformation passes. There is some trickiness in that GVN's
ValueNumber class requires hand holding to get to compile cleanly. I'm
open to suggestions about a better pattern there, but I tried several
before settling on this. I was trying to balance my desire to sink as
much implementation detail into the source file as possible without
introducing overly many layers of abstraction.

Much like with SROA, the design of this system is made somewhat more
cumbersome by the need to support both pass managers without duplicating
the significant state and logic of the pass. The same compromise is
struck here.

I've also left a FIXME in a doxygen comment as the GVN pass seems to
have pretty woeful documentation within it. I'd like to submit this with
the FIXME and let those more deeply familiar backfill the information
here now that we have a nice place in an interface to put that kind of
documentaiton.

Differential Revision: http://reviews.llvm.org/D18019

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263208 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 08:50:55 +00:00
Matt Arsenault
6da276af59 AMDGPU: Don't use InstVisitor for AMDGPUPromoteAlloca
Frontend authors are strongly encouraged to keep allocas
in the entry block, so don't bother visiting every instruction
in the other blocks of the function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263206 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 08:20:50 +00:00
Matt Arsenault
7137d0dce6 AMDGPU: R600 code splitting cleanup
Move a few functions only used by R600 to R600 specific code,
fix header macros to stop using R600, mark classes as final.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263204 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 08:00:27 +00:00
Hrvoje Varga
55b6a233ae [mips] Invalid tests for MTC0, MTC2, MFC0, MFC2, DMTC0, DMFC0 MIPS instructions
Differential Revision: http://reviews.llvm.org/D18037


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263203 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 08:00:11 +00:00
Matt Arsenault
e4e707f153 AMDGPU: Materialize sign bits with bfrev
If a constant is the same as the reverse of an inline immediate,
this is 4 bytes smaller than having to embed a 32-bit literal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263201 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 07:42:49 +00:00
Junmo Park
abc3287851 Minor code cleanups. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263200 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 07:05:32 +00:00
Junmo Park
c1b22faefa Minor code cleanup. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263196 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 05:07:07 +00:00
Pete Cooper
1ac3fbac0f Remove llvm::getDISubprogram in favor of Function::getSubprogram
llvm::getDISubprogram walks the instructions in a function, looking for one in the scope of the current function, so that it can find the !dbg entry for the subprogram itself.

Now that !dbg is attached to functions, this should not be necessary. This patch changes all uses to just query the subprogram directly on the function.

Ideally this should be NFC, but in reality its possible that a function:

has no !dbg (in which case there's likely a bug somewhere in an opt pass), or
that none of the instructions had a scope referencing the function, so we used to not find the !dbg on the function but now we will

Reviewed by Duncan Exon Smith.

Differential Revision: http://reviews.llvm.org/D18074

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263184 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 02:14:16 +00:00
Evgeniy Stepanov
85c673d5c9 [gold] Fix common symbols handling.
LLVM Gold plugin decides which instance of a common symbol it wants
based on the symbol size in claim_file_hook. If the file that
contains the chosen instance is later dropped from the link, we end
up with an undefined reference.

This change delays this decision until the set of the included files
is known.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263180 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 00:51:57 +00:00
Adam Nemet
18d2ee844e [LLE] Add missed LoopSimplify dependence
The code assumed that we always had a preheader without making the pass
dependent on LoopSimplify.

Thanks to Mattias Eriksson V for reporting this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263173 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 23:54:39 +00:00
Tim Northover
32048586b0 AArch64: only try to use scaled fcvt ops on legal vector types.
Before we ended up calling getSimpleVectorType on a <3 x float>, which
asserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263169 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 23:02:21 +00:00
Sanjay Patel
444e7f9783 [x86] don't use a shuffle when a vselect will do; NFCI
Looking at the IR definition of a masked load made me realize
there was no reason to use a shuffle here, so we don't need
to convert the format of the mask at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263167 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 22:35:33 +00:00
Marianne Mailhot-Sarrasin
578acc5b53 Test commit access
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263165 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 21:54:25 +00:00
Simon Pilgrim
bbb1dbaaca Strip trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263162 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 20:58:11 +00:00
Simon Pilgrim
86875b1fdf [X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG
Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns.

Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion).

Differential Revision: http://reviews.llvm.org/D17691

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263159 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 20:40:26 +00:00
Artur Pilipenko
980df33d17 Support arbitrary addrspace pointers in masked load/store intrinsics
This patch fixes the problem which occurs when loop-vectorize tries to use @llvm.masked.load/store intrinsic for a non-default addrspace pointer. It fails with "Calling a function with a bad signature!" assertion in CallInst constructor because it tries to pass a non-default addrspace pointer to the pointer argument which has default addrspace.

The fix is to add pointer type as another overloaded type to @llvm.masked.load/store intrinsics.

Reviewed By: reames

Differential Revision: http://reviews.llvm.org/D17270


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263158 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 20:39:22 +00:00
Peter Collingbourne
c593fadd95 ARM: Support relative references using the PREL31 symbol variant.
Differential Revision: http://reviews.llvm.org/D17937

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263156 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 19:30:18 +00:00
Balaram Makam
21374d486c Fix testicase to turn buildbot green. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263154 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 19:07:50 +00:00
Nicolai Haehnle
5dae380620 [TableGen] more helpful error message in MapTableEmitter
Differential Revision: http://reviews.llvm.org/D17275

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263148 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 18:51:58 +00:00
Teresa Johnson
b738b28f97 Materialize metadata in IRLinker before value mapping
Summary:
Unless we plan to do later postpass metadata linking (ThinLTO special mode),
always invoke metadata materialization at the start of IRLinker::run().
This avoids the need for clients who use lazy metadata loading to
explicitly invoke materializeMetadata before the IRMover, which in
turn invokes IRLinker::run and needs materialized metadata for mapping.

Came up in the context of an LLD issue (D17982).

Reviewers: rafael

Subscribers: silvas, llvm-commits

Differential Revision: http://reviews.llvm.org/D17992

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263143 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 18:47:03 +00:00
Tim Northover
07f1262d8a AArch64: remove pseudo-instructions used only for their patterns.
There's no real reason for these pseudos to exist, we should be writing real
patterns even if it is slightly less convenient. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263141 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 18:46:12 +00:00
Nicolai Haehnle
f0eb7094d4 AMDGPU/SI: add llvm.amdgcn.buffer.load/store.format intrinsics
Summary:
They correspond to BUFFER_LOAD/STORE_FORMAT_XYZW and will be used by Mesa
to implement the GL_ARB_shader_image_load_store extension.

The intention is that for llvm.amdgcn.buffer.load.format, LLVM will decide
whether one of the _X/_XY/_XYZ opcodes can be used (similar to image sampling
and loads). However, this is not currently implemented.

For llvm.amdgcn.buffer.store, LLVM cannot decide to use one of the "smaller"
opcodes and therefore the intrinsic is overloaded. Currently, only the v4f32
is actually implemented since GLSL also only has a vec4 variant of the store
instructions, although it's conceivable that Mesa will want to be smarter
about this in the future.

BUFFER_LOAD_FORMAT_XYZW is already exposed via llvm.SI.vs.load.input, which
has a legacy name, pretends not to access memory, and does not capture the
full flexibility of the instruction.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D17277

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263140 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 18:43:50 +00:00
Michael Kuperstein
b448651c49 [X86] Correctly select registers to pop into for x86_64
When trying to replace an add to esp with pops, we need to choose dead
registers to pop into. Registers clobbered by the call and not imp-def'd
by it should be safe. Except that it's not enough to check the register
itself isn't defined, we also need to make sure no overlapping registers
are defined either.

This fixes PR26711.

Differential Revision: http://reviews.llvm.org/D18029

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263139 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 18:43:21 +00:00
Balaram Makam
e99741c2d5 [AArch64] Optimize compare and branch sequence when the compare's constant operand is power of 2
Summary:
Peephole optimization that generates a single TBZ/TBNZ instruction
for test and branch sequences like in the example below. This handles
the cases that miss folding of AND into TBZ/TBNZ during ISelLowering of BR_CC

Examples:
   and  w8, w8, #0x400
   cbnz w8, L1
 to
   tbnz w8, #10, L1

Reviewers: MatzeB, jmolloy, mcrosier, t.p.northover

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D17942

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263136 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 17:54:55 +00:00
Sanjay Patel
3ad244cde2 give regression test a meaningful name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263135 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 17:52:19 +00:00
Alexandros Lamprineas
b4bb1d1359 [ARM] Cortex-R8 support
This patch adds Cortex-R8 to Target Parser and TableGen.
It also adds CodeGen tests for the build attributes.

Patch by Pablo Barrio.

Differential Revision: http://reviews.llvm.org/D17925

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263132 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 17:38:41 +00:00
Mehdi Amini
fffed50461 Rename -discard-value-names into -lto-discard-value-names in libLLVMLTO
This is avoiding a naming conflict with opt and llc.
While opt and llc don't link to LTO usually, users that are building a
monolithic libLLVM.dylib and linking the tools to it would have a
runtime error because of the duplicate cl::opt registration.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263127 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 17:06:52 +00:00
Changpeng Fang
de01cf1028 AMDGPU/SI: Define S_GETREG Intrinsic
Summary:
 Define s_getreg intrinsic to generate s_getreg instruction to read
hardware registers.

Reviewers: tstellarAMD, arsenm

Subscribers: llvm-commits, arsenm

Differential Revision: http://reviews.llvm.org/D17892

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263124 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 16:47:15 +00:00
Saleem Abdulrasool
9dd2ef1cf2 ARM: follow up improvements for SVN r263118
The initial change was insufficiently complete for always getting the semantics
of __builtin_longjmp correct.  The builtin is translated into a
`tInt_eh_sjlj_longjmp` DAG node.  This node set R7 as clobbered.  However, the
code would then follow up with a clobber of R11.  I had failed to notice the
imp-def,kill on R7 in the isel.  Unfortunately, it seems that it is not possible
to conditionalise the Defs list via an !if.  Instead, construct a new parallel
WIN node and prefer that when targeting windows.  This ensures that we now both
correctly model the __builtin_longjmp as well as construct the frame in a more
ABI conformant manner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263123 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 16:26:37 +00:00
Chandler Carruth
ffadaf5667 [SROA] Fix PR25873, which Andrea Di Biagio analyzed the daylights out
of, and I misdiagnosed for months and months.

Andrea has had a patch for this forever, but I just couldn't see how
it was fixing the root cause of the problem. It didn't make sense to me,
even though the patch was perfectly good and the analysis of the actual
failure event was *fantastic*.

Well, I came back to it today because the patch has sat for *far* too
long and needs attention and decided I wouldn't let it go until I really
understood what was going on. After quite some time in the debugger,
I finally realized that in fact I had just missed an important case with
my previous attempt to fix PR22093 in r225149. Not only do we need to
handle loads that won't be split, but stores-of-loads that we won't
split. We *do* actually have enough logic in the presplitting to form
new slices for split stores.... *unless* we decided not to split them!

I'm so sorry that it took me this long to come to the realization that
this is the issue. It seems so obvious in hind sight (of course).
Anyways, the fix becomes *much* smaller and more focused. The fact that
we're left doing integer smashing is related to the FIXME in my original
commit: fundamentally, we're not aggressive about pre-splitting for
loads and stores to the same alloca. If we want to get aggressive about
this, it'll need both what Andrea had put into the proposed fix, but
also a *lot* more logic to essentially iteratively pre-split the alloca
until we can't do any more. As I said in that commit log, its really
unclear that this is the right call. Instead, the integer blending and
letting targets lower this to narrower stores seems slightly better. But
we definitely shouldn't really go down that path just to fix this bug.

Again, tons of thanks are owed to Andrea and others at Sony for working
on this bug. I really should have seen what was going on here and
re-directed them sooner. =////

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263121 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 15:31:17 +00:00
David L Kreitzer
ce75835901 Unified the handling of returns in the X87 stackifier so that the stackifier
runs successfully on routines containing IRETs. This fixes PR26410.

Differential Revision: http://reviews.llvm.org/D17643


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263120 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 15:14:02 +00:00
NAKAMURA Takumi
7b7de7dc81 Fixup for r263114. llvm::AnalysisBase<CallGraphAnalysis> should be declared as extern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263119 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 15:13:00 +00:00
Saleem Abdulrasool
b3f28fc50b ARM: correct __builtin_longjmp on WoA
WoA uses r11 as the FP even though it is a pure thumb-2 environment in contrast
to AAPCS which states r7.  This adjusts __builtin_longjmp to not clobber r7 and
to properly restore the frame pointer on execution.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263118 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 15:11:09 +00:00
Chandler Carruth
53fa006c35 [CG] Back out my pointless move ctor and add the explicit template
instantiation needed for the mingw dll build bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263114 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 14:33:10 +00:00
Chandler Carruth
df383be7e5 [SROA] Clean up some really weird code, no functionality changed.
We already have the instruction extracted into 'I', just cast that to
a store the way we do for loads. Also, we don't enter the if unless SI
is non-null, so don't test it again for null.

I'm pretty sure the entire test there can be nuked, but this is just the
trivial cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263112 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 14:16:18 +00:00
Elena Demikhovsky
7d23bb996b AVX-512: Fixed a bug in i1 vector zero extending. (Skylake-avx512)
(failed on instruction selection phase)

Differential Revision: http://reviews.llvm.org/D17924



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263111 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 13:44:22 +00:00
Chandler Carruth
77d9151731 [CG] Try adding an explicit move constructor to see if that helps the
one build bot that is crashing on this code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263110 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 13:43:06 +00:00
Valery Pykhtin
134ae13a5d [AMDGPU] Fix SMEM instructions encoding/operand namings
Differential Revision: http://reviews.llvm.org/D17651

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263108 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 13:06:08 +00:00
Simon Pilgrim
c21bed9d78 [X86][AVX] Improve target shuffle combining of BLEND+zero
The BLEND+zero combine was failing to combine equivalent BLEND masks.

Follow up to D17483 and D17858

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263105 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 11:50:15 +00:00
Chandler Carruth
f1b2c7b945 [CG] Add a new pass manager printer pass for the old call graph and
actually finish wiring up the old call graph.

There were bugs in the old call graph that hadn't been caught because it
wasn't being tested. It wasn't being tested because it wasn't in the
pipeline system and we didn't have a printing pass to run in tests. This
fixes all of that.

As for why I'm still keeping the old call graph alive its so that I can
port GlobalsAA to the new pass manager with out forking it to work with
the lazy call graph. That's clearly the right eventual design, but it
seems pragmatic to defer that until its necessary. The old call graph
works just fine for GlobalsAA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263104 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 11:24:11 +00:00
Chandler Carruth
c9fd7655a0 [LCG] Spell the printing pass pipeline name for the lazy call graph
'lcg' instead of just 'cg'.

This makes it consistent with the analysis name of 'lcg'.

No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263103 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 11:24:06 +00:00
Simon Pilgrim
eda788c7b7 [X86][SSE] Basic combining of unary target shuffles of binary target shuffles.
This patch reorders the combining of target shuffle masks so that when a unary shuffle takes a binary shuffle as its input but only references one of its inputs it can correctly combine into a unary shuffle mask.

This is starting to encroach on the purpose of resolveTargetShuffleInputs, but I don't want to remove it until we definitely know we won't need it for full binary shuffle combining.

There is a lot more work before we can properly support binary target shuffle masks but this was an easy case to add support for.

Differential Revision: http://reviews.llvm.org/D17858

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263102 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 11:23:51 +00:00
Chandler Carruth
7a06f63f10 [CG] Actually hoist up the generic CallGraphPrinter pass from a weird
location in the opt tool to live along side the analysis in LLVM's
libraries.

No functionality changed here, but this will allow me to port the
printer to the new pass manager as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263101 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 11:08:44 +00:00
Chandler Carruth
562873f9be [CG] Rename the DOT printing pass to actually reference "DOT".
There is another pass by the generic name 'CallGraphPrinter' which is
actually just a call graph printer tucked away inside the opt tool. I'd
like to bring it out and make it follow the same patterns as the rest of
the CallGraph code, but doing so would end up conflicting with the name
of the DOT printing pass. So this makes the DOT printing pass name be
more precise.

No functionality changed here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263100 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 11:04:40 +00:00
Elena Demikhovsky
4196f55435 AVX-512: Fixed a bug in shuffle for v64i8 type
Operation SCALAR_TO_VECTOR for v64i8 and v32i16 should be lowered if BW feature is "on".

Differential Revision: http://reviews.llvm.org/D17994



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263097 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 08:32:09 +00:00
Vedant Kumar
ee68a6ce38 [opt] Fix description of the -disable-verify flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263096 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 06:58:53 +00:00
Mark Lacey
2a9c5591ed Add an LLVM_BUILTIN_DEBUGTRAP macro.
Summary:
This provides a macro that expands to __builtin_debugtrap() for clang,
and __debugbreak() for MSVC.

It intentionally expands to nothing for compilers that do not support a
similar mechanism that halts the debugger without otherwise crashing the
process.

Differential Revision: http://reviews.llvm.org/D18002

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263095 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 05:15:03 +00:00
Roman Levenstein
c461035332 Add support for a preserve_most calling convention to the AArch64 backend.
This change adds a support for a preserve_most calling convention to the AArch64 backend, similar to how it was done for X86-64.

There is also a subsequent patch on top of this one to add a tail-calls support for this calling convention.

Differential Revision: http://reviews.llvm.org/D18016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263092 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-10 04:35:09 +00:00