Commit Graph

147638 Commits

Author SHA1 Message Date
Zachary Turner
ab480f45cd [Support] Add support for unique_ptr<> to Casting.h.
Often you have a unique_ptr<T> where T supports LLVM's
casting methods, and you wish to cast it to a unique_ptr<U>.
Prior to this patch, this requires doing hacky things like:

unique_ptr<U> Casted;
if (isa<U>(Orig.get()))
  Casted.reset(cast<U>(Orig.release()));

This is overly verbose, and it would be nice to just be able
to use unique_ptr directly with cast and dyn_cast.  To this end,
this patch updates cast<> to work directly with unique_ptr<T>,
so you can now write:

auto Casted = cast<U>(std::move(Orig));

Since it's possible for dyn_cast<> to fail, however, we choose
to use a slightly different API here, because it's awkward to
write

if (auto Casted = dyn_cast<U>(std::move(Orig))) {}

when Orig may end up not having been moved at all.  So the
interface for dyn_cast is

if (auto Casted = unique_dyn_cast<U>(Orig)) {}

Where the inclusion of `unique` in the name of the cast operator
re-affirms that regardless of success of or fail of the casting,
exactly one of the input value and the return value will contain
a non-null result.

Differential Revision: https://reviews.llvm.org/D31890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300098 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 19:59:37 +00:00
Zachary Turner
12e38cb73b Remove svnprop eol-style:native from Casting.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300096 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 19:52:47 +00:00
Craig Topper
d0d13f5774 [InstCombine] Teach SimplifyMultipleUseDemandedBits to handle And/Or/Xor known bits using the LHS/RHS known bits it already acquired without recursing back into computeKnownBits.
This replicates the known bits and constant creation code from the single use case for these instructions and adds it here. The computeKnownBits and constant creation code for other instructions is now in the default case of the opcode switch.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300094 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 19:32:47 +00:00
Craig Topper
1db7e25e94 [InstCombine] Remove unreachable code for turning an And where all demanded bits on both sides are known to be zero into a constant 0.
We already handled a superset check that included the known ones too and folded to a constant that may include ones. But it can also handle the case of no ones.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300093 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 19:08:03 +00:00
Sanjay Patel
2c5adb18ba [InstCombine] fix wrong undef handling when converting select to shuffle
As discussed in:
https://bugs.llvm.org/show_bug.cgi?id=32486
...the canonicalization of vector select to shufflevector does not hold up
when undef elements are present in the condition vector. 

Try to make the undef handling clear in the code and the LangRef.

Differential Revision: https://reviews.llvm.org/D31980



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300092 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:39:53 +00:00
Craig Topper
c5de42f38f [SelectionDAG] Use APInt move assignment to avoid 2 memory allocations and copies when bit width is larger than 64-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300091 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:39:27 +00:00
Kyle Butt
718593b3f9 CodeGen: BlockPlacement: Add comment about DenseMap Safety.
The use of a DenseMap in precomputeTriangleChains does not cause
non-determinism, even though it is iterated over, as the only thing the
iteration does is to insert entries into a new DenseMap, which is not iterated.
Comment only change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300088 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:30:32 +00:00
Peter Collingbourne
1c404b475d llvm-lto2: Add a dump-symtab subcommand.
This allows us to test the symbol table APIs for LTO input files.

Differential Revision: https://reviews.llvm.org/D31920

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300086 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:27:00 +00:00
Craig Topper
d9096c7391 [InstCombine] In SimplifyMultipleUseDemandedBits, use a switch instead of cascaded ifs on opcode. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300085 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:25:25 +00:00
Craig Topper
51f7e1a9dc [InstCombine] Teach SimplifyDemandedInstructionBits that even if we reach an instruction that has multiple uses, if we know all the bits for the demanded bits for this context we can go ahead and create a constant.
Currently if we reach an instruction with multiples uses we know we can't do any optimizations to that instruction itself since we only have the demanded bits for one of the users. But if we know all of the bits are zero/one for that one user we can still go ahead and create a constant to give to that user.

This might then reduce the instruction to having a single use and allow additional optimizations on the other path.

This picks up an additional case that r300075 didn't catch.

Differential Revision: https://reviews.llvm.org/D31552



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300084 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:17:46 +00:00
Matthias Braun
6b814345d1 MachineScheduler: Skip acyclic latency heuristic for in-order cores
The current heuristic is triggered on `InFlightCount > BufferLimit`
which isn't really helpful on in-order cores where BufferLimit is zero.

Note that we already get latency hiding effects for in order cores
by instructions staying in the pending queue on stalls; The additional
latency scheduling heuristics only have minimal effects after that while
occasionally increasing register pressure too much resulting in extra
spills.

My motivation here is additional spills/reloads ending up in a loop in
464.h264ref / BlockMotionSearch function resulting in a 4% overal
regression on an in order core. rdar://30264380

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300083 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:09:05 +00:00
Craig Topper
c7bad98e0e [InstCombine] Move portion of SimplifyDemandedUseBits that deals with instructions with multiple uses out to a separate method. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300082 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:05:21 +00:00
Renato Golin
73ba5e9415 [SystemZ] Fix more target specific tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300081 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 18:03:09 +00:00
Renato Golin
3183fbc849 [SystemZ] Fix target specific tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300078 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 17:14:46 +00:00
Dmitry Preobrazhensky
b4ede06cc4 [AMDGPU][MC] Added support for several VI-specific opcodes (s_wakeup, etc)
Added support for VI:

- s_endpgm_saved
- s_wakeup
- s_rfe_restore_b64
- v_perm_b32

Enabled for VI:

- v_mov_fed_b32
- v_mov_fed_b32_e64

See bug 32593: https://bugs.llvm.org//show_bug.cgi?id=32593

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D31931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300076 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 17:10:07 +00:00
Craig Topper
3461e9c2e4 Teach SimplifyDemandedUseBits that adding or subtractings 0s from every bit below the highest demanded bit can be simplified
If we are adding/subtractings 0s below the highest demanded bit we can just use the other operand and remove the operation.

My primary motivation is observing that we can call ShrinkDemandedConstant for the add/sub and create a 0 constant, rather than removing the add completely. In the case I saw, we modified the constant on an add instruction to a 0, but the add is not put into the worklist. So we didn't revisit it until the next InstCombine iteration. This caused an IR modification to remove add and a subsequent iteration to be ran.

With this change we get bypass the add in the first iteration and prevent the second iteration from changing anything.

Differential Revision: https://reviews.llvm.org/D31120



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300075 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 16:49:59 +00:00
Dmitry Preobrazhensky
ef86a1e6af [AMDGPU][MC] Corrected parsing of v_cmp_class* and v_cmpx_class*
Fixed bug 32565: https://bugs.llvm.org//show_bug.cgi?id=32565

Reviewers: vpykhtin

Differential Revision: https://reviews.llvm.org/D31820

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300073 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 16:31:18 +00:00
Derek Schuff
490024c934 [WebAssembly] Update use of Attributes after r299875
This fixes the failing WebAssemblyLowerEmscriptenEHSjLj tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300072 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 16:03:00 +00:00
Dmitry Preobrazhensky
405c945bb5 [AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CI
Corrected encoding of V_MQSAD_U32_U8 for CI

See bug 32552: https://bugs.llvm.org//show_bug.cgi?id=32552

Reviewers: vpykhtin

Differential Revision: https://reviews.llvm.org/D31810

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300070 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 15:36:09 +00:00
Easwaran Raman
6f3228cc82 Fix the bootstrap failure caused by r299986.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300069 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 15:26:15 +00:00
Sanjay Patel
e930b092c4 [InstCombine] morph an existing instruction instead of creating a new one
One potential way to make InstCombine (very slightly?) faster is to recycle instructions 
when possible instead of creating new ones. It's not explicitly stated AFAIK, but we don't
consider this an "InstSimplify". We could, however, make a new layer to house transforms 
like this if that makes InstCombine more manageable (just throwing out an idea; not sure 
how much opportunity is actually here).

Differential Revision: https://reviews.llvm.org/D31863


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300067 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 15:11:33 +00:00
Dmitry Preobrazhensky
df5e51ce8f [AMDGPU][MC] Corrected ds_wrxchg2* to support two offsets
Fixed bug 28227: https://bugs.llvm.org//show_bug.cgi?id=28227

Reviewers: vpykhtin

Differential Revision: https://reviews.llvm.org/D31808

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300066 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 14:29:45 +00:00
Jonas Paulsson
c2dad95b1e Fix a RUN line in new test.
Use '2>&1 |' and not '|&' to pipe debug output to FileCheck

Hopefully handles a "shell parser error" on
llvm-clang-x86_64-expensive-checks-win

test/Transforms/SLPVectorizer/SystemZ/SLP-cmp-cost-query.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300064 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 14:25:08 +00:00
Serge Pavlov
e4957d5a3e Remove redundant type casts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300063 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 14:13:00 +00:00
Ed Maste
944d939ce1 Fix detection of backtrace() availability on FreeBSD
On FreeBSD backtrace is not part of libc and depends on libexecinfo
being available. Instead of using manual checks we can use the builtin
CMake module FindBacktrace.cmake to detect availability of backtrace()
in a portable way.

Patch By:	Alex Richardson
Differential Revision:	https://reviews.llvm.org/D27143


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300062 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 13:51:00 +00:00
Jonas Paulsson
0b09474fe1 [SLPVectorizer] Pass the right type argument to getCmpSelInstrCost()
In getEntryCost(), make the scalar type for a compare instruction that of the
operands, not i1. This is needed in order to call getCmpSelInstrCost() for a
compare in a sensible way, the same way as the LoopVectorizer does.

New test: test/Transforms/SLPVectorizer/SystemZ/SLP-cmp-cost-query.ll

Review: Matthew Simpson
https://reviews.llvm.org/D31601

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300061 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 13:29:25 +00:00
Benjamin Kramer
4e5abdf67c [MachineBlockPlacment] Add an assert to ensure there is no order dependency on DenseMap iteration order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300060 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 13:26:31 +00:00
Benjamin Kramer
2b37175e41 [MachineBlockPlacement] Clean up data structures a bit.
No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300059 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 13:26:28 +00:00
Jonas Paulsson
16b23e95d5 [LoopVectorizer] Improve handling of branches during cost estimation.
The cost for a branch after vectorization is very different depending on if
the vectorizer will if-convert the block (branch is eliminated), or if
scalarized and predicated blocks will be produced (branch duplicated before
each block). There is also the case of remaining scalar branches, such as the
back-edge branch.

This patch handles these cases differently with TTI based cost estimates.

Review: Matthew Simpson
https://reviews.llvm.org/D31175

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300058 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 13:13:15 +00:00
Igor Breger
e353fb8d83 [GlobalIsel][X86] support G_CONSTANT selection.
Summary: [GlobalISel][X86] support G_CONSTANT selection. Add regbank select tests.

Reviewers: zvi, guyblank

Reviewed By: guyblank

Subscribers: llvm-commits, dberris, rovka, kristof.beyls

Differential Revision: https://reviews.llvm.org/D31974

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300057 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 12:54:54 +00:00
Jonas Paulsson
43d439da88 [LoopVectorizer, TTI] New method supportsEfficientVectorElementLoadStore()
Since SystemZ supports vector element load/store instructions, there is no
need for extracts/inserts if a vector load/store gets scalarized.

This patch lets Target specify that it supports such instructions by means of
a new TTI hook that defaults to false.

The use for this is in the LoopVectorizer getScalarizationOverhead() method,
which will with this patch produce a smaller sum for a vector load/store on
SystemZ.

New test: test/Transforms/LoopVectorize/SystemZ/load-store-scalarization-cost.ll

Review: Adam Nemet
https://reviews.llvm.org/D30680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300056 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 12:41:37 +00:00
Dmitry Preobrazhensky
fcce15e390 [AMDGPU][MC] Corrected src0 size for s_cbranch_join
Fix for bug 28159: https://bugs.llvm.org//show_bug.cgi?id=28159

Reviewers: vpykhtin, arsenm

Differential Revision: https://reviews.llvm.org/D31595

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300055 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 12:40:19 +00:00
Jonas Paulsson
2778098e17 [SystemZ] Updated test fp-cast.ll
This did not get included in the previous commit for SystemZ cost functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300053 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 12:11:41 +00:00
Jonas Paulsson
c33bdfa7b1 [SystemZ] TargetTransformInfo cost functions implemented.
getArithmeticInstrCost(), getShuffleCost(), getCastInstrCost(),
getCmpSelInstrCost(), getVectorInstrCost(), getMemoryOpCost(),
getInterleavedMemoryOpCost() implemented.

Interleaved access vectorization enabled.

BasicTTIImpl::getCastInstrCost() improved to check for legal extending loads,
in which case the cost of the z/sext instruction becomes 0.

Review: Ulrich Weigand, Renato Golin.
https://reviews.llvm.org/D29631

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300052 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 11:49:08 +00:00
Krasimir Georgiev
6120b8f9e9 [DWARF] Fix compiler warnings in DWARFContext.cpp, NFCi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300051 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 11:33:26 +00:00
Piotr Padlewski
715890b279 [LangRef] fix documentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300050 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 11:18:19 +00:00
Sam Kolton
9a421935fb [AMDGPU] SDWA: make pass global
Summary: Remove checks for basic blocks.

Reviewers: vpykhtin, rampitec, arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D31935

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300040 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 09:36:05 +00:00
George Rimar
2b0a45f335 [DWARF] - Refactoring of DWARFContextInMemory implementation.
This change is basically relative to D31136, where I initially wanted to
implement some relocations handling optimization which shows it can give
significant boost. Though even without any caching algorithm looks
code can have some cleanup at first.

Refactoring separates out code for taking symbol address, used in relocations
computation.

Differential revision: https://reviews.llvm.org/D31747

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300039 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 08:59:15 +00:00
Chandler Carruth
76dc6181d8 [IR] Rename the class templates for the case iterator and case handle to
not collide with the naming convention for template *arguments*. In at
least one case they actually collided and this confuses MSVC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300038 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 08:48:39 +00:00
Daniel Sanders
81de2d08ab [globalisel][tablegen] Add experimental support for OperandWithDefaultOps, PredicateOperand, and OptionalDefOperand
Summary:
As far as instruction selection is concerned, all three appear to be same thing.

Support for these operands is experimental since AArch64 doesn't make use
of them and the in-tree targets that do use them (AMDGPU for
OperandWithDefaultOps, AMDGPU/ARM/Hexagon/Lanai for PredicateOperand, and ARM
for OperandWithDefaultOps) are not using tablegen-erated GlobalISel yet.

Reviewers: rovka, aditya_nandakumar, t.p.northover, qcolombet, ab

Reviewed By: rovka

Subscribers: inglorion, aemerson, rengolin, mehdi_amini, dberris, kristof.beyls, igorb, tpr, llvm-commits

Differential Revision: https://reviews.llvm.org/D31135

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300037 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 08:23:08 +00:00
Bjorn Pettersson
a22205806d [LoadCombine] Avoid analysing dead basic blocks
Summary:
Dead basic blocks may be forming a loop, for which SSA form is
fulfilled, but with a circular def-use chain. LoadCombine could
enter an infinite loop when analysing such dead code. This patch
solves the problem by simply avoiding to analyse all basic blocks
that aren't forward reachable, from function entry, in LoadCombine.

Fixes https://bugs.llvm.org/show_bug.cgi?id=27065

Reviewers: mehdi_amini, chandlerc, grosser, Bigcheese, davide

Reviewed By: davide

Subscribers: dberlin, zzheng, bjope, grandinj, Ka-Ka, materi, jholewinski, llvm-commits, mzolotukhin

Differential Revision: https://reviews.llvm.org/D31032

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300034 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 08:07:55 +00:00
Piotr Padlewski
3512d22fea Invariant.group and mustalias docs fixes
Summary:
Alias analysis would like to know that
invariant.group.barrier returns pointer that mustalias,
but this can't imply that we can replace one pointer with another

Reviewers: dberlin, sanjoy

Subscribers: llvm-commits, chandlerc, hfinkel, nlewycky, amharc

Differential Revision: https://reviews.llvm.org/D31758

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300033 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 07:59:35 +00:00
Chandler Carruth
ddfada260a [IR] Redesign the case iterator in SwitchInst to actually be an iterator
and to expose a handle to represent the actual case rather than having
the iterator return a reference to itself.

All of this allows the iterator to be used with common STL facilities,
standard algorithms, etc.

Doing this exposed some missing facilities in the iterator facade that
I've fixed and required some work to the actual iterator to fully
support the necessary API.

Differential Revision: https://reviews.llvm.org/D31548

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300032 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 07:27:28 +00:00
Craig Topper
00b79068c4 [IR] Fix copy and paste mistake in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300031 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 05:57:46 +00:00
Craig Topper
96d92eadca [InstCombine][IR] Add a commutable BinOp matcher. Use it to reduce some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300030 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 05:49:28 +00:00
Serguei Katkov
4f5f4e9e2a [BPI] Refactor post domination calculation and simple fix for ColdCall
Collection of PostDominatedByUnreachable and PostDominatedByColdCall have been
split out of heuristics itself. Update of the data happens now for each basic
block (before update for PostDominatedByColdCall might be skipped if
unreachable or matadata heuristic handled this basic block).

This separation allows re-ordering of heuristics without loosing
the post-domination information.

Reviewers: sanjoy, junbuml, vsk, chandlerc, reames

Reviewed By: chandlerc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31701


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300029 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 05:42:14 +00:00
Serguei Katkov
81e9372c9e [INC] Test commit. NFC.
Just an update of comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300026 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 04:41:35 +00:00
Kannan Narayanan
d3302ddc52 [AMDGPU] Add a new pass to insert waitcnts. Leave under an option for testing.
Based on comments in https://reviews.llvm.org/D31161.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300023 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 03:25:12 +00:00
Kyle Butt
92625cfb47 CodeGen: BlockPlacement: Clear ComputedEdges between functions.
Not clearing was causing non-deterministic compiles for large files. Addresses
for MachineBasicBlocks would end up colliding and we would lay out a block that
we assumed had been pre-computed when it had not been.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300022 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 03:18:20 +00:00
Bob Haarman
4a0d76ba2f ThinLTOBitcodeWriter: keep comdats together, rename if leader is renamed
Summary:
COFF requires that every comdat contain a symbol with the same name as
the comdat. ThinLTOBitcodeWriter renames symbols, which may cause this
requirement to be violated. This change avoids such violations by
renaming comdats if their leaders are renamed. It also keeps comdats
together when splitting modules.

Reviewers: pcc, mehdi_amini, tejohnson

Reviewed By: pcc

Subscribers: rnk, Prazek, llvm-commits

Differential Revision: https://reviews.llvm.org/D31963


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300019 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-12 01:43:07 +00:00