131585 Commits

Author SHA1 Message Date
Daniel Sanders
8bc041ce85 [mips][ias] Attempt to fix 'not all control paths return a value' reported by MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268927 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 15:37:52 +00:00
Frederic Riss
856a0143b0 [dsymutil] Prevent use-after-free
The BinaryHolder would query the archive member MemoryBuffer name
to check if the current open archive also contains the next requested
objectfile. This comparison was using a StringRef to a temporary
buffer. It only happened with fat archives. This commit adds long-lived
storage along with the MemoryBuffers for the fat archive filename.

The added test would fail during an ASAN build without the fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268924 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 14:44:14 +00:00
Joerg Sonnenberger
ee2078606f Optimize a printf with a double procent to putchar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268922 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 14:36:16 +00:00
James Molloy
ec0b9c8745 [VectorUtils] Query number of sign bits to allow more truncations
When deciding if a vector calculation can be done in a smaller bitwidth, use sign bit information from ValueTracking to add more information and allow more truncations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268921 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 14:32:30 +00:00
Daniel Sanders
43d2886cca [mips][micromips] Make getPointerRegClass() result depend on the instruction.
Summary:
Previously, it returned the GPR16MMRegClass for all instructions which was
incorrect for instructions like lwsp/lwgp and unnecesarily restricted the
permitted registers for instructions like lw32.

This fixes quite a few of the -verify-machineinstrs errors reported in PR27458.
I've only added -verify-machineinstrs to one test in this change since I
understand there is a plan to enable the verifier by default.

Reviewers: hvarga, zbuljan, zoran.jovanovic, sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D19873

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268918 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 13:38:25 +00:00
Rafael Espindola
0c06716f89 Fix bug where temporary file would be left behind every time an archive was updated.
When updating an existing archive, llvm-ar opens the old archive into a
`MemoryBuffer`, does its thing, and writes the results to a temporary
file. That file is then renamed to the original archive filename, thus
replacing it with the updated contents. However, on Windows at least,
what would happen is that the `MemoryBuffer` for the old archive would
actually be an mmap'ed view of the file, so when it came time to do the
rename via Win32's `ReplaceFile`, it would succeed but would be unable
to fully replace the file since there would still be a handle open on
it; instead, the old version got renamed to a random temporary name and
left behind.

Patch by Cameron!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268916 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 13:31:11 +00:00
Simon Pilgrim
0f420ada79 [X86][SSE] Added TODO comment to add support for AVX512 mask registers to shuffle comments
This came up in discussion on D19198

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268915 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 13:30:16 +00:00
Daniel Sanders
b2292f8443 [mips] Fix use after free and an unnecessary copy introduced in r268896.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268913 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 13:10:57 +00:00
Strahinja Petrovic
a16fdea51a [PowerPC] fix register alignment for long double type
This patch fixes register alignment for long double type in
soft float mode. Before this patch alignment was 8 and this
patch changes it to 4.
Differential Revision: http://reviews.llvm.org/D18034



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268909 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 12:27:39 +00:00
Chris Dewhurst
e06fb6bce7 [Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargets
This change adds SMAC (signed multiply-accumulate) and UMAC (unsigned multiply-accumulate) for LEON subtargets of the Sparc processor.

The new files LeonFeatures.td and leon-instructions.ll will both be expanded in future, so I want to leave them separate as small files for this review, to be expanded in future check-ins.

Note: The functions are provided only for inline-assembly provision. No DAG selection is provided.

Differential Revision: http://reviews.llvm.org/D19911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268908 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 11:55:15 +00:00
Silviu Baranga
784cb3fef6 [AArch64] Implement lowering of the X constraint on AArch64
Summary:
This implements the lowering of the X constraint on
AArch64.

The default behaviour of the X constraint lowering is to
restrict it to "f". This is a problem because the "f"
constraint is not implemented on AArch64 and would be too
restrictive anyway. Therefore, the AArch64 hook will
lower this to "w" (if the operand is a floating point or
vector) or "r" otherwise.

The implementation is similar with the one added for
ARM (r267411).

This is the AArch64 side of the fix for http://llvm.org/PR26493

Reviewers: rengolin

Subscribers: aemerson, rengolin, llvm-commits, t.p.northover

Differential Revision: http://reviews.llvm.org/D19967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268907 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 11:10:44 +00:00
Simon Pilgrim
a5df424f08 [X86][AVX512] Added masked version of combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268904 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 10:43:13 +00:00
Benjamin Kramer
bc38c49428 Revert "[Mips] Fix use after free."
Fixes use after free but breaks tests.

This reverts commit r268901.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268902 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 10:31:17 +00:00
Benjamin Kramer
04c6ebbe71 [Mips] Fix use after free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268901 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 10:21:56 +00:00
Daniel Sanders
0b6e0490cf [mips][ias] R_MIPS_(GOT|HI|LO|PC)16 and R_MIPS_GPREL32 do not need symbols.
Summary:
In theory, care must be taken to ensure that pairs of R_MIPS_(GOT|HI|LO)16
make the same decision on both relocs in the reloc pair but in practice
this isn't as hard as it sounds and only limits the complexity of the
predicate used. We handle all three with the same code to ensure their
decisions always agree with each other.

Reviewers: sdardis

Subscribers: rafael, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19016


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268900 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 10:21:14 +00:00
Zlatko Buljan
dc02050702 [mips][microMIPS] Implement LWP and SWP instructions
Differential Revision: http://reviews.llvm.org/D10640


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268896 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 08:07:28 +00:00
Frederic Riss
c0fdf88ac7 [dsymutil] Fix -arch option for thumb variants.
r267249 removed the dual ARM/Thumb interface from MachOObjectFile,
simplifying llvm-dsymutil's code. This unfortunately also regressed
llvm-dsymutil's ability to select thumb slices, because the simplified
code was also dealing with the discrepency between the slice arch
(eg. armv7m) and the triple arch name (eg. thumbv7m).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268894 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 06:01:12 +00:00
Craig Topper
3c29a695f2 [X86] Strengthen some type contraints for floating point round and extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268892 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 05:34:14 +00:00
Craig Topper
63eccc2eca [AVX512] Fix up types for arguments of int_x86_avx512_mask_cvtsd2ss_round and int_x86_avx512_mask_cvtss2sd_round. Only the argument being converted should be a different type. The other 2 argument should have the same type as the result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268891 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 05:34:12 +00:00
Mehdi Amini
437f2fc22e ThinLTOCodeGenerator: ignore 0 values for the cache settings.
From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268890 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 05:16:30 +00:00
Craig Topper
84a0ca551e [AVX512] Add non-temporal store patterns for v16i32/v32i16/v64i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268889 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 23:43:17 +00:00
Junmo Park
328324434e Minor code cleanups. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268888 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 23:22:58 +00:00
Craig Topper
f453dfba6f [AVX512] Add missing patterns for non-temporal stores of 128/256-bit vXi8/vXi16/vXi32 when VLX is enabled. The equivalent AVX1/2 patterns are disabled by VLX.
This caused regular stores to be emitted instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268886 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 23:08:45 +00:00
Craig Topper
5cb772fb8a [AVX512] Change predicates on some vXi16/vXi8 AVX store patterns so they stay enabled unless VLX and BWI instructions are supported."
Without this we could fail instruction selection if VLX was enabled, but BWI wasn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268885 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 23:08:40 +00:00
Craig Topper
dba67a4fdb [AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX encoded VPXORD so all 32 registers can be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268884 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 21:33:53 +00:00
Craig Topper
605a46a88d [X86] Re-generate tests using update_llc_test_checks.py to prepare for a future commit. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268883 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 21:33:47 +00:00
Craig Topper
79c01a2d3e Remove Windows line endings in some tests to prepare for a future commit. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268882 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 21:33:44 +00:00
Bruno Cardoso Lopes
2b1f6c23bc [Bitcode] Fix an unsigned integer overflow while parsing bitcode wrapper header
Specially crafted bitcode wrapper headers can cause unsigned interger
overflow and lead to crashes when wrapping around. Fix the offset check
and avoid such scenarios.

Writing a testcase for this would involve editing the binary to generate
values that trigger the overflow, since this would never happen while
generating the bitcode in regular compilation flows, so there's
currently no feasible way add one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268881 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 21:27:39 +00:00
Craig Topper
ba458cf29f [X86] Remove extra patterns that check for BUILD_VECTOR of all 0s. These are always canonicalized to v4i32/v8i32/v16i32 except for in SSE1 only when only v4f32 is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268880 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 20:10:20 +00:00
Simon Pilgrim
ba60f16656 [CostModel][X86] Extended comparison instruction cost model tests to include SSE2/SSE3/SSSE3/SSE41/SSE42 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268877 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 15:24:53 +00:00
David Majnemer
aa09aeb5c0 [X86] Promote several single precision FP libcalls on Windows
A number of libcalls don't exist in any particular lib but are, instead,
defined in math.h as inline functions (even in C mode!).  Don't rely on
their existence when lowering @llvm.{cos,sin,floor,..}.f32, promote them
instead.

N.B. We had logic to handle FREM but were missing out on a number of
others.  This change generalizes the FREM handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268875 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 08:15:50 +00:00
Craig Topper
82b3d2dd64 [X86] Lower 256-bit vector all-zero constants to v8i32 even with AVX1 only. Either way a 256-bit VXORPS will be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268873 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 07:10:54 +00:00
Craig Topper
7e89a31db3 [X86] Add patterns for 256-bit non-temporal stores when only AVX1 is supported. While there, add a predicate to the SSE2 patterns to avoid an ordering dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268872 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 07:10:50 +00:00
Craig Topper
16942ada10 [X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when only AVX1 is supported. AVX_SET0 just expands to 256-bit VXORPS which is legal in AVX1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268871 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 07:10:47 +00:00
Weiming Zhao
a9ffc49ea9 [ARM] Fix Scavenger assert due to underestimated stack size
(re-apply r268810 as it exposed an uninitialized variable in ARM MFI.
 Patch 268868 should fix that.)

Summary:
Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure.

Reviewers: rengolin

Subscribers: vitalybuka, aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits

Differential Revision: http://reviews.llvm.org/D19896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268869 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 05:11:54 +00:00
Weiming Zhao
4e54474603 Fix use-of-uninitialized-value of ARMMachineFunctionInfo
Summary: Explicitly initialize ArgumentStackSize to prevent the msan failure.

Reviewers: rengolin

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D20051

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268868 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 05:04:47 +00:00
Simon Pilgrim
0c91669b71 Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268867 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 20:19:59 +00:00
Simon Pilgrim
e5f67907d9 [SelectionDAG] Added bitreverse(bitreverse(v)) --> v
Added bitreverse creation testing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268865 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 20:12:36 +00:00
Craig Topper
fe2a4e4f58 [X86] Fix InstAliases to not allow FARCALL32i/FARCALL16i/FARJMP32i/FARJMP16i in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268863 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 19:25:56 +00:00
Simon Pilgrim
5528905e3b [X86] Added BITREVERSE constant folding and identity tests
Identity tests are currently failing - this will be fixed soon

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268862 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 19:04:00 +00:00
Simon Pilgrim
d2bfb61994 [X86] Pulled out duplicate mask width calculation. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268861 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 18:04:24 +00:00
Simon Pilgrim
a3ea594334 [CostModel][X86] Split BSWAP/BITREVERSE cost tests from CTPOP/CTLZ/CTTZ 'bit count' cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268859 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 16:34:16 +00:00
Sanjay Patel
2f183e0a89 [x86, BMI] add TLI hook for 'andn' and use it to simplify comparisons
For the sake of minimalism, this patch is x86 only, but I think that at least
PPC, ARM, AArch64, and Sparc probably want to do this too.

We might want to generalize the hook and pattern recognition for a target like
PPC that has a full assortment of negated logic ops (orc, nand).

Note that http://reviews.llvm.org/D18842 will cause this transform to trigger
more often.

For reference, this relates to:
https://llvm.org/bugs/show_bug.cgi?id=27105
https://llvm.org/bugs/show_bug.cgi?id=27202
https://llvm.org/bugs/show_bug.cgi?id=27203
https://llvm.org/bugs/show_bug.cgi?id=27328

Differential Revision: http://reviews.llvm.org/D19087



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268858 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 15:03:40 +00:00
NAKAMURA Takumi
074a68d30b ErrorInfoBase::message(): Don't use raw_string_ostream's buffer, Msg, before closing. Use raw_string_ostream::str() to flush the buffer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268856 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 08:43:11 +00:00
Xinliang David Li
f05d4a7577 [PM] code refactoring -- preparation for new PM porting /NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268851 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 05:39:12 +00:00
Mehdi Amini
0c3421d8d9 Fix stripDebugInfo: was modifying "DebugLoc" attached to the intrinsic after deleting it.
Fix MSAN build.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268849 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 05:07:47 +00:00
NAKAMURA Takumi
2dea119616 MipsELFObjectWriter.cpp: Activate debug printer just for +Asserts. [-Wunused-function]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268848 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 04:51:51 +00:00
Mehdi Amini
79941185c0 Refactor stripDebugInfo(Function) to handle intrinsic
This moves the code that handles stripping debug info intrinsic from
 StripDebugInfo(Module) to StripDebugInfo(Function). The latter is
already walking every instructions so it makes sense to do it at the
same time.
This makes also stripDebugInfo(Function) as an API more useful: it
is really dropping every debug info in the Function.
Finally the existing code is trigerring an assertion when the Module
is not fully materialized.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268847 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 04:10:52 +00:00
Lang Hames
e7679f2715 [Orc] Fix missing rename from r268845.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268846 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 03:48:56 +00:00
Lang Hames
c14b8e9703 [Orc] Rename OrcArchitectureSupport to OrcABISupport and add Win32 ABI support.
This enables lazy JITing on Windows x86-64.

Patch by David. Thanks David!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268845 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 03:36:38 +00:00