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a860b189e4
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51798 Commits

Author SHA1 Message Date
Chad Rosier
a860b189e4 Add support for lowering fneg when AVX is enabled. 
rdar://10566486


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 01:02:25 +00:00
Pete Cooper
4e5a1ab10b Added InstCombine for "select cond, ~cond, x" type patterns 
These can be reduced to "~cond & x" or "~cond | x"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146624 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 00:56:45 +00:00
Owen Anderson
4e0adfa7f7 Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. These are already marked as illegal by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146623 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 00:54:12 +00:00
Eli Friedman
7d1ff37118 Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146621 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 00:50:34 +00:00
Bill Wendling
7a13b72bbb Re-re-enable compact unwind after fixing a failure in SingleSource/Benchmarks/Shootout-C++/except.cpp and friends. It was encoding the stored registers in the wrong order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146617 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 00:14:24 +00:00
Kevin Enderby
dac2953e3b Another improvement to the implementation of .incbin directive by avoiding a 
buffer copy.  Suggestion by Chris Lattner!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146614 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 00:00:27 +00:00
Bill Wendling
10e412ec6b The saved registers weren't being processed in the correct order. This lead to 
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146612 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:53:24 +00:00
Dan Gohman
f042660197 Move Instruction::isSafeToSpeculativelyExecute out of VMCore and 
into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146610 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:49:11 +00:00
Jakob Stoklund Olesen
299b059cd6 Consider CPE alignment in CreateNewWater(). 
An aligned constant pool entry may require extra alignment padding where
the new water is created.  Take that into account when computing offset.

Also consider the alignment of other constant pool entries when
splitting a basic block.  Alignment padding may make it necessary to
move the split point higher.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146609 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:48:54 +00:00
Jim Grosbach
799ca9d1b7 ARM NEON better assembly operand range checking for lane indices of VLD/VST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:35:06 +00:00
Jim Grosbach
9b1b390288 ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:25:46 +00:00
Devang Patel
5211134fbd Do not sink instruction, if it is not profitable. 
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.

Radar 10266272.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146604 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:20:38 +00:00
Bill Wendling
69fdcd7f90 Reapply r146481 with a fix to create the Builder value in the correct place and 
with the correct iterator.
<rdar://problem/10530851>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146600 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 22:45:33 +00:00
Kevin Enderby
c3fc3136a1 Improve the implementation of .incbin directive by replacing a loop by using 
getStreamer().EmitBytes.  Suggestion by Benjamin Kramer!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 22:34:45 +00:00
Andrew Trick
19154f4576 LSR: Fold redundant bitcasts on-the-fly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146597 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 22:07:19 +00:00
Jim Grosbach
ec04a3f8db ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:49:24 +00:00
Kevin Enderby
c55accaddb Add the .incbin directive which takes the binary data from a file and emits 
it to the streamer.  rdar://10383898


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:47:48 +00:00
Jim Grosbach
2dbab5c33d Nuke old code. Missed in last commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146590 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:41:32 +00:00
Jim Grosbach
bb3a2e4d0d ARM NEON refactor VST2 w/ writeback instructions. 
In addition to improving the representation, this adds support for assembly
parsing of these instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:32:11 +00:00
Jim Grosbach
20accfc6c7 ARM NEON improve factoring a bit. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 20:59:15 +00:00
Evan Cheng
020f4106f8 Model ARM predicated write as read-mod-write. e.g. 
r0 = mov #0
r0 = moveq #1

Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 20:00:08 +00:00
Jim Grosbach
e90ac9bce9 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 19:35:22 +00:00
Stepan Dyatkovskiy
ac12ef4ad2 Fix for bug #11429: Wrong behaviour for switches. Small improvement for code size heuristics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 19:19:17 +00:00
Dan Gohman
f9096e450b It turns out that clang does use pointer-to-function types to 
point to ARC-managed pointers sometimes. This fixes rdar://10551239.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146577 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 19:10:53 +00:00
Jakob Stoklund Olesen
5e46dcbb4b Fix speling and 80-col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 18:49:13 +00:00
Akira Hatanaka
3faac0a78c Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object 
emission is not supported yet, but a patch that adds the support should follow
soon.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146572 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 18:26:41 +00:00
Jim Grosbach
5dca1c9f63 Fix copy/pasto that skipped the 'modify' step. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146571 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 18:12:37 +00:00
Jim Grosbach
4677708d4f ARM/Thumb2 mov vs. mvn alias goes both ways. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 17:56:51 +00:00
Chad Rosier
6762f8f302 VFP2 is required for FP loads. Noticed by inspection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146569 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 17:55:03 +00:00
Chad Rosier
64ac91b4b6 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146568 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 17:32:02 +00:00
Jim Grosbach
8d11c6349f ARM/Thumb2 'cmp rn, #imm' alias to cmn. 
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 17:30:24 +00:00
Chad Rosier
404ed3c223 Fix 80-column violation and extraneous brackets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 17:26:05 +00:00
NAKAMURA Takumi
d2cda5ce51 llvm/lib/CodeGen: Fix cmake build since r146542. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 03:50:53 +00:00
Eli Friedman
e6109828d7 Fix a stupid typo in MemDepPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146549 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:54:39 +00:00
Eli Friedman
e08db65c48 Add missing cases to SDNode::getOperationName(). Patch by Micah Villmow. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146548 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:28:54 +00:00
Evan Cheng
12dfdb424d Allow target to specify register output dependency. Still default to one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146547 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:28:53 +00:00
Bill Wendling
dbdc616ed5 Revert r146481 to review possible miscompilations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146546 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:18:26 +00:00
Bill Wendling
e08643be3a Disable to review some failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146545 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:16:54 +00:00
Jim Grosbach
a39cda7aff ARM assembler support for the target-specific .req directive. 
rdar://10549683


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:16:11 +00:00
Evan Cheng
ddfd1377d2 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function 
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 02:11:42 +00:00
Nick Lewycky
798313d6c1 DW_AT_virtuality is also defined to be constant, not flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146534 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 00:56:07 +00:00
Chad Rosier
c6cff9daf4 Per discussion on the list, remove BitcodeVerify pass to reimplement as a free function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146531 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 00:29:31 +00:00
Kostya Serebryany
bd7910d158 [asan] remove .preinit_array from the compiler module (it breaks .so builds). This should be done in the run-time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146527 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 00:01:51 +00:00
Michael J. Spencer
5b08230930 Support/FileSystem: Add file_magic and move a vew clients over to it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146523 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 23:17:12 +00:00
Michael J. Spencer
b92cb30cf5 Support/Program: Make Change<stream>ToBinary return error_code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 23:16:49 +00:00
Michael J. Spencer
faebf11a34 Cleanup whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146521 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 23:16:15 +00:00
Jim Grosbach
863d2af947 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 22:45:11 +00:00
Jim Grosbach
27debd60a1 ARM LDM/STM system instruction variants. 
rdar://10550269

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:48:29 +00:00
Jim Grosbach
b0659873e6 Thumb2 pre/post indexed stores can be from any non-PC GPR. 
rdar://10549786

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:10:25 +00:00
Jim Grosbach
d7ea73a490 Thumb2 tweak for ccout handling in RSB parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146516 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:06:41 +00:00