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42 Commits

Author SHA1 Message Date
Bill Schmidt
70273be423 [PowerPC] Flow oversized lines for r235309 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235310 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-20 15:58:46 +00:00
Bill Schmidt
54f902e367 [PowerPC] Add future work for vector insert/extract to README_ALTIVEC.txt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235309 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-20 15:54:26 +00:00
Ed Maste
ffc045ab80 Correct 'teh' and other typos / repeated words. 
Patch by Eitan Adler.

Differential Revision:	http://reviews.llvm.org/D8514


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234939 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-14 20:52:58 +00:00
Kit Barton
c5860523be Updated with list of possible improvements we are tracking internally 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231946 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-11 17:43:43 +00:00
Nemanja Ivanovic
b69d556c37 Add LLVM support for PPC cryptography builtins 
Review: http://reviews.llvm.org/D7955


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231285 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-04 20:44:33 +00:00
Kit Barton
40057e8ee8 Add the following 64-bit vector integer arithmetic instructions added in POWER8: 
vaddudm
vsubudm
vmulesw
vmulosw
vmuleuw
vmulouw
vmuluwm
vmaxsd
vmaxud
vminsd
vminud
vcmpequd
vcmpequd.
vcmpgtsd
vcmpgtsd.
vcmpgtud
vcmpgtud.
vrld
vsld
vsrd
vsrad

Phabricator review: http://reviews.llvm.org/D7959


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231115 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-03 19:55:45 +00:00
Chris Lattner
7c400dcb03 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50267 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-25 17:25:00 +00:00
Nate Begeman
b5041b3085 readme updates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47051 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-13 07:06:12 +00:00
Chris Lattner
e481e8bc8f Add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27999 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 00:04:05 +00:00
Chris Lattner
8cc5ffb27f add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27832 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-19 16:22:38 +00:00
Chris Lattner
bf9b3716ed add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27828 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-19 05:55:06 +00:00
Chris Lattner
87140126e8 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27809 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-18 18:30:19 +00:00
Chris Lattner
90564f26d1 Implement an important entry from README_ALTIVEC: 
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's.  Instead, just branch on CR6 directly. :)

For example, for:
void foo2(vector float *A, vector float *B) {
  if (!vec_any_eq(*A, *B))
    *B = (vector float){0,0,0,0};
}

We now generate:

_foo2:
        mfspr r2, 256
        oris r5, r2, 12288
        mtspr 256, r5
        lvx v2, 0, r4
        lvx v3, 0, r3
        vcmpeqfp. v2, v3, v2
        bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
        vxor v2, v2, v2
        stvx v2, 0, r4
        mtspr 256, r2
        blr
LBB1_2: ; UnifiedReturnBlock
        mtspr 256, r2
        blr

instead of:

_foo2:
        mfspr r2, 256
        oris r5, r2, 12288
        mtspr 256, r5
        lvx v2, 0, r4
        lvx v3, 0, r3
        vcmpeqfp. v2, v3, v2
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        cmpwi cr0, r3, 0
        beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
        vxor v2, v2, v2
        stvx v2, 0, r4
        mtspr 256, r2
        blr
LBB1_2: ; UnifiedReturnBlock
        mtspr 256, r2
        blr

This implements CodeGen/PowerPC/vec_br_cmp.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-18 17:59:36 +00:00
Chris Lattner
3be29059ab move some stuff around, clean things up 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-18 17:52:36 +00:00
Chris Lattner
19a815238e Implement v16i8 multiply with this code: 
vmuloub v5, v3, v2
        vmuleub v2, v3, v2
        vperm v2, v2, v5, v4

This implements CodeGen/PowerPC/vec_mul.ll.  With this, v16i8 multiplies are
6.79x faster than before.

Overall, UnitTests/Vector/multiplies.c is now 2.45x faster with LLVM than with
GCC.

Remove the 'integer multiplies' todo from the README file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27792 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-18 03:57:35 +00:00
Chris Lattner
22fcbb1320 remove done item 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27778 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-17 21:52:03 +00:00
Chris Lattner
966083fd1a add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27758 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-17 17:29:41 +00:00
Chris Lattner
5913810b82 Implement a TODO: for any shuffle that can be viewed as a v4[if]32 shuffle, 
if it can be implemented in 3 or fewer discrete altivec instructions, codegen
it as such.  This implements Regression/CodeGen/PowerPC/vec_perf_shuffle.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27748 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-17 05:28:54 +00:00
Chris Lattner
f3f69decca Implement a TODO: have the legalizer canonicalize a bunch of operations to 
one type (v4i32) so that we don't have to write patterns for each type, and
so that more CSE opportunities are exposed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27731 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-16 01:37:57 +00:00
Chris Lattner
b17f1679e3 Make the BUILD_VECTOR lowering code much more aggressive w.r.t constant vectors. 
Remove some done items from the todo list.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27729 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-16 01:01:29 +00:00
Chris Lattner
ed93790517 add a note, move an altivec todo to the altivec list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27654 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-13 16:48:00 +00:00
Chris Lattner
ac225ca051 Add a new way to match vector constants, which make it easier to bang bits of 
different types.

Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1.  This compiles:

typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
  *P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
  *P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
  *P3 = vec_abs((vector float)*P3);
}

to:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        vspltisw v0, -1
        vslw v0, v0, v0
        lvx v1, 0, r3
        vand v1, v1, v0
        stvx v1, 0, r3
        lvx v1, 0, r4
        vandc v1, v1, v0
        stvx v1, 0, r4
        lvx v1, 0, r5
        vandc v0, v1, v0
        stvx v0, 0, r5
        mtspr 256, r2
        blr

instead of (with two constant pool entries):

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        li r6, lo16(LCPI1_0)
        lis r7, ha16(LCPI1_0)
        li r8, lo16(LCPI1_1)
        lis r9, ha16(LCPI1_1)
        lvx v0, r7, r6
        lvx v1, 0, r3
        vand v0, v1, v0
        stvx v0, 0, r3
        lvx v0, r9, r8
        lvx v1, 0, r4
        vand v1, v1, v0
        stvx v1, 0, r4
        lvx v1, 0, r5
        vand v0, v1, v0
        stvx v0, 0, r5
        mtspr 256, r2
        blr

GCC produces (with 2 cp entries):

_test:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc00c
        mtspr 256,r0
        lis r2,ha16(LC0)
        lis r9,ha16(LC1)
        la r2,lo16(LC0)(r2)
        lvx v0,0,r3
        lvx v1,0,r5
        la r9,lo16(LC1)(r9)
        lwz r12,-4(r1)
        lvx v12,0,r2
        lvx v13,0,r9
        vand v0,v0,v12
        stvx v0,0,r3
        vspltisw v0,-1
        vslw v12,v0,v0
        vandc v1,v1,v12
        stvx v1,0,r5
        lvx v0,0,r4
        vand v0,v0,v13
        stvx v0,0,r4
        mtspr 256,r12
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27624 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-12 19:07:14 +00:00
Chris Lattner
95c7570f32 we have a shuffle instr, add an example. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27592 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-11 18:47:03 +00:00
Chris Lattner
1c80103016 Add an item 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27470 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-06 23:16:19 +00:00
Chris Lattner
116cc48e30 Pattern match vmrg* instructions, which are now lowered by the CFE into shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27457 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-06 21:11:54 +00:00
Chris Lattner
58d665c182 remove two done items 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27453 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-06 19:19:38 +00:00
Chris Lattner
d0608e191f Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to 
lower it and LLVM to have one fewer intrinsic.  This implements
CodeGen/PowerPC/vec_shuffle.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27450 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-06 18:26:28 +00:00
Chris Lattner
d8242b49b2 Add all of the data stream intrinsics and instructions. woo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27442 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-05 22:27:14 +00:00
Chris Lattner
0d2cf6b1d1 add vmladduhm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27423 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-05 00:49:48 +00:00
Chris Lattner
8b4684247a add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27419 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-04 23:45:11 +00:00
Chris Lattner
298b684229 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27414 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-04 22:43:55 +00:00
Chris Lattner
02b72556d7 Remove done item 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27351 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 05:28:54 +00:00
Chris Lattner
c55bfd0265 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27348 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 03:59:11 +00:00
Chris Lattner
9f7e127133 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27302 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 19:00:22 +00:00
Chris Lattner
4468c22458 Implement an item from the readme, folding vcmp/vcmp. instructions with 
identical instructions into a single instruction.  For example, for:

void test(vector float *x, vector float *y, int *P) {
  int v = vec_any_out(*x, *y);
  *x = (vector float)vec_cmpb(*x, *y);
  *P = v;
}

we now generate:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v0, v1, v0
        mfcr r4, 2
        stvx v0, 0, r3
        rlwinm r3, r4, 27, 31, 31
        xori r3, r3, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

instead of:

_test:
        mfspr r2, 256
        oris r6, r2, 57344
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v2, v1, v0
        mfcr r4, 2
***     vcmpbfp v0, v1, v0
        rlwinm r4, r4, 27, 31, 31
        stvx v0, 0, r3
        xori r3, r4, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

Testcase here: CodeGen/PowerPC/vcmp-fold.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27290 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 06:02:07 +00:00
Chris Lattner
8f5d316ff2 These are done 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27284 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 04:53:21 +00:00
Chris Lattner
f3a627262c add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27243 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 00:24:13 +00:00
Chris Lattner
d732a2915b add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27227 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 18:56:23 +00:00
Nate Begeman
98e70cc124 Add a few more altivec intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27215 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 04:15:58 +00:00
Chris Lattner
ecc219b8d4 implement a bunch more intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27209 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:29:37 +00:00
Chris Lattner
3ee9ffb0e5 Add a bunch of notes from my journey thus far. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27170 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 07:41:00 +00:00
Chris Lattner
b86bd2cee2 Split out altivec notes into their own README 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27168 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 07:04:16 +00:00