Commit Graph

101936 Commits

Author SHA1 Message Date
Joel Jones
bd2e6e0b1a [Mips] Document Mips Backend Relocation Principles
This revision documents the combination of C++ and table-gen code that
handles relocations and addresses.

Thanks for Simon Dardis for the careful reviews.

Differential Revision: https://reviews.llvm.org/D31628


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300986 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 14:49:27 +00:00
Chad Rosier
3ad4f88821 [AArch64][Falkor] Refine resource needs of STRQ with register offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300984 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 14:33:13 +00:00
Matthew Simpson
915a4bc0f9 [LV] Model if-converted phi node costs
Phi nodes in non-header blocks are converted to select instructions after
if-conversion. This patch updates the cost model to account for the selects.

Differential Revision: https://reviews.llvm.org/D31906

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300980 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 14:14:54 +00:00
Daniel Sanders
9eb6db17b6 Revert r300964 + r300970 - [globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.
It's causing llvm-clang-x86_64-expensive-checks-win to fail to compile and I
haven't worked out why. Reverting to make it green while I figure it out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300978 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 14:09:20 +00:00
Sanjay Patel
bd1b03d467 [InstCombine] prefer xor with -1 because 'not' is easier to understand (PR32706)
This matches the demanded bits behavior in the DAG and should fix:
https://bugs.llvm.org/show_bug.cgi?id=32706

Differential Revision: https://reviews.llvm.org/D32255


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300977 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 14:03:54 +00:00
Chad Rosier
f9f7441f9c [AArch64][Falkor] Refine loads/stores that require an extra LD pipe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300976 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 13:55:41 +00:00
Chad Rosier
01a74846f0 [AArch64][Falkor] Fix number of microops for WriteSTIdx missed in r300892.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300975 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 13:37:01 +00:00
Chad Rosier
da9c35ab22 [AArch64] Fix a few missed pre/post-inc in Falkor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300974 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 13:36:57 +00:00
Diana Picus
2fe29b4914 [ARM] GlobalISel: Add support for G_TRUNC
Select them as copies. We only select if both the source and the
destination are on the same register bank, so this shouldn't cause any
trouble.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300971 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 13:16:50 +00:00
Diana Picus
17c66f84bb [ARM] GlobalISel: Make struct arguments fail elegantly
The condition in isSupportedType didn't handle struct/array arguments
properly. Fix the check and add a test to make sure we use the fallback
path in this kind of situation. The test deals with some common cases
where the call lowering should error out. There are still some issues
here that need to be addressed (tail calls come to mind), but they can
be addressed in other patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300967 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 11:53:01 +00:00
Daniel Sanders
d3ed5b78e5 [globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.
Summary:
The SelectionDAG importer now imports rules with Predicate's attached via
Requires, PredicateControl, etc. These predicates are implemented as
bitset's to allow multiple predicates to be tested together. However,
unlike the MC layer subtarget features, each target only pays for it's own
predicates (e.g. AArch64 doesn't have 192 feature bits just because X86
needs a lot).

Both AArch64 and X86 derive at least one predicate from the MachineFunction
or Function so they must re-initialize AvailableFeatures before each
function. They also declare locals in <Target>InstructionSelector so that
computeAvailableFeatures() can use the code from SelectionDAG without
modification.

Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab

Reviewed By: rovka

Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D31418

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300964 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 10:27:20 +00:00
Clement Courbet
de3d17e6c2 typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300963 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 09:21:05 +00:00
Clement Courbet
69190edbb9 use repmovsb when optimizing forminsize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300960 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 09:20:55 +00:00
Clement Courbet
e5aaed5aca Rename FastString flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300959 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 09:20:50 +00:00
Clement Courbet
3b883555dd X86 memcpy: use REPMOVSB instead of REPMOVS{Q,D,W} for inline copies
when the subtarget has fast strings.

This has two advantages:
  - Speed is improved. For example, on Haswell thoughput improvements increase
    linearly with size from 256 to 512 bytes, after which they plateau:
    (e.g. 1% for 260 bytes, 25% for 400 bytes, 40% for 508 bytes).
  - Code is much smaller (no need to handle boundaries).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300957 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 09:20:39 +00:00
George Rimar
102d78ca39 [DWARF] - Refactoring: localize handling of relocations in a single place.
This is splitted from D32228,
currently DWARF parsers code has few places that applied relocations values manually.
These places has similar duplicated code. Patch introduces separate method that can be
used to obtain relocated value. That helps to reduce code and simplifies things.

Differential revision: https://reviews.llvm.org/D32284

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300956 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 09:12:18 +00:00
Clement Courbet
9b72933cb9 Delete dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300952 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 07:40:59 +00:00
Artyom Skrobov
3e7dae893c [Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing Uses = [CPSR]
Summary: Thanks to Oliver Stannard for helping catch this.

Reviewers: olista01, efriedma

Subscribers: llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D31815

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300951 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 07:35:21 +00:00
Serguei Katkov
9bb6c3a55b [AsmWriter] Eliminate warning. NFC
This patch eliminates the following warning

lib/IR/AsmWriter.cpp:1128:57: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
                 (StrVal[1] >= '0' && StrVal[1] <= '9')) &&

Reviewers: timshen, rnk, davide
Reviewed By: davide
Subscribers: davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D32337


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300950 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 06:14:38 +00:00
George Burgess IV
67bc67ffea [MSSA] Clean up the updater a bit. NFC
- Mark an internal function static
- Remove the llvm namespace (just holding on to the `using namespace
  llvm;` Works on My Machine(TM))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300947 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 04:54:52 +00:00
Davide Italiano
1b5b740e23 [PartialInliner] Fix crash when inlining functions with unreachable blocks.
CodeExtractor looks up the dominator node corresponding to return blocks
when splitting them. If one of these blocks is unreachable, there's no
node in the Dom and CodeExtractor crashes because it doesn't check
for domtree node validity.
In theory, we could add just a check for skipping null DTNodes in
`splitReturnBlock` but the fix I propose here is slightly different. To the
best of my knowledge, unreachable blocks are irrelevant for the algorithm,
therefore we can just skip them when building the candidate set in the
constructor.

Differential Revision:  https://reviews.llvm.org/D32335

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300946 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 04:25:00 +00:00
Serguei Katkov
c849a0cc07 [AsmWriter/APFloat] FP constant printing: Avoid usage of locale dependent snprinf
This should fix the bug https://bugs.llvm.org/show_bug.cgi?id=12906

To print the FP constant AsmWriter does the following:

  1) convert FP value to String (actually using snprintf function which is locale dependent).
  2) Convert String back to FP Value
  3) Compare original and got FP values. If they are not equal just dump as hex.

The problem happens on the 2nd step when APFloat does not expect group delimiter or
fraction delimiter other than period symbol and so on, which can be produced on the
first step if LLVM library is used in an environment with corresponding locale set.

To fix this issue the locale independent APFloat:toString function is used.
However it prints FP values slightly differently than snprintf does. Specifically
it suppress trailing zeros in significant, use capital E and so on.
It results in 117 test failures during make check.
To avoid this I've also updated APFloat.toString a bit to pass make check at least.

Reviewers: sberg, bogner, majnemer, sanjoy, timshen, rnk

Reviewed By: timshen, rnk

Subscribers: rnk, llvm-commits

Differential Revision: https://reviews.llvm.org/D32276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300943 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 02:52:17 +00:00
Akira Hatanaka
1933132d0a Revert r300932 and r300930.
It seems that r300930 was creating an infinite loop in dag-combine when
compling the following file:

MultiSource/Benchmarks/MiBench/consumer-typeset/z21.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300940 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 01:31:50 +00:00
Akira Hatanaka
2159c695f3 [AArch64] Use suffix ULL to shift a 64-bit value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300932 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 00:35:27 +00:00
Davide Italiano
f113d04b8d [CodeExtractor] Remove an unneeded level of indirection. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300931 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 00:21:09 +00:00
Akira Hatanaka
63da689bdf [AArch64] Improve code generation for logical instructions taking
immediate operands.

This commit adds an AArch64 dag-combine that optimizes code generation
for logical instructions taking immediate operands. The optimization
uses demanded bits to change a logical instruction's immediate operand
so that the immediate can be folded into the immediate field of the
instruction.

This recommits r300913, which broke bots because I didn't fix a call to
ShrinkDemandedConstant in SIISelLowering.cpp after changing the APIs of
TargetLoweringOpt and TargetLowering.

rdar://problem/18231627

Differential Revision: https://reviews.llvm.org/D5591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300930 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-21 00:05:16 +00:00
Eli Friedman
df4849c1dd Revert r300746 (SCEV analysis for or instructions).
There have been multiple reports of this causing problems: a
compile-time explosion on the LLVM testsuite, and a stack
overflow for an opencl kernel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300928 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 23:59:05 +00:00
Craig Topper
c7e3512b43 [InstCombine] Remove the zextOrTrunc from ShrinkDemandedConstant.
The demanded mask and the constant should always be the same width for all callers today.

Also stop copying the demanded mask as its passed in. We should avoid allocating memory unless we are going to do something. The final AND to create the new constant will take care of it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300927 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 23:58:27 +00:00
Matthias Braun
e0bfbeae68 X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFC
X86RegisterInfo::eliminateFrameIndex() and
X86FrameLowering::getFrameIndexReference() both had logic to compute the
base register. This consolidates the code.

Also use MachineInstr::isReturn instead of manually enumerating tail
call instructions (return instructions were not included in the previous
list because they never reference frame indexes).

Differential Revision: https://reviews.llvm.org/D32206

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300923 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 23:34:50 +00:00
Matthias Braun
6ef1610d07 X86RegisterInfo: eliminateFrameIndex: Force SP for AfterFPPop; NFC
AfterFPPop is used for tailcall/tailjump instructions. We shouldn't ever
have frame-pointer/base-pointer relative addressing for those. After all
the frame/base pointer should already be restored to their previous
values at the return.

Make this fact explicit in preparation for an upcoming refactoring.

Differential Revision: https://reviews.llvm.org/D32205

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300922 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 23:34:46 +00:00
Akira Hatanaka
01c014ca98 Revert "[AArch64] Improve code generation for logical instructions taking"
This reverts r300913.

This broke bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300916 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 23:03:30 +00:00
Akira Hatanaka
ac0ecde9f0 [AArch64] Improve code generation for logical instructions taking
immediate operands.

This commit adds an AArch64 dag-combine that optimizes code generation
for logical instructions taking immediate operands. The optimization
uses demanded bits to change a logical instruction's immediate operand
so that the immediate can be folded into the immediate field of the
instruction.

rdar://problem/18231627

Differential Revision: https://reviews.llvm.org/D5591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300913 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 22:47:56 +00:00
Sanjay Patel
f23a493cab [InstCombine] function names start with lower-case letter; NFC
Forgot to make this fix with the signature change in r300911.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300912 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 22:37:01 +00:00
Sanjay Patel
e29c6aab81 [InstCombine] allow shl+shr demanded bits folds with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300911 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 22:33:54 +00:00
Tim Northover
efa8c0e73a AArch64: lower "fence singlethread" to a pure compiler barrier.
Single-threaded fences aren't required to provide any synchronization with
other processing elements so there's no need for a DMB. They should still be a
barrier for compiler optimizations though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300905 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 21:57:45 +00:00
Tim Northover
ff268972fc ARM: lower "fence singlethread" to a pure compiler barrier.
Single-threaded fences aren't required to provide any synchronization with
other processing elements so there's no need for a DMB. They should still be a
barrier for compiler optimizations though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300904 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 21:56:52 +00:00
Xinliang David Li
2747b70917 Use basicblock split block utility function
Instead of calling BasicBlock::SplitBasicBlock directly in 
CodeExtractor.

Differential Revision: https://reviews.llvm.org/D32308


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300899 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 21:40:22 +00:00
Sanjay Patel
a24f137360 [InstCombine] allow shl demanded bits folds with splat constants
More fixes are needed to enable the helper SimplifyShrShlDemandedBits().



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300898 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 21:33:02 +00:00
Craig Topper
7b99ac1139 [InstCombine] Use APInt::intersects and APInt::isSubsetOf to improve a few more places in SimplifyDemandedBits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300896 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 21:24:37 +00:00
Chad Rosier
9ec21444cc [AArch64] Whitespace/ordering fixes for Falkor machine description. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300893 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 21:11:17 +00:00
Chad Rosier
4b046c4cf4 [AArch64] Refine Falkor machine description for pre/post-inc and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300892 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 21:11:09 +00:00
Sanjay Patel
f0d51838c5 [InstCombine] allow ashr/lshr demanded bits folds with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300888 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 20:59:02 +00:00
Craig Topper
a6180c4b3c [InstCombine] Use APInt::isSubsetOf to simplify some code in SimplifyDemandedBits. NFC
This allows us to use less temporary APInt for And and Invert operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300885 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 20:47:35 +00:00
Adrian Prantl
52a72dacab Don't emit locations that need a DW_OP_stack_value in DWARF 2 & 3.
https://bugs.llvm.org/show_bug.cgi?id=32382

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300883 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 20:42:33 +00:00
Tim Northover
8cc396e7aa ARM: handle post-indexed NEON ops where the offset isn't the access width.
Before, we assumed that any ConstantInt offset was precisely the access width,
so we could use the "[rN]!" form. ISelLowering only ever created that kind, but
further simplification during combining could lead to unexpected constants and
incorrect codegen.

Should fix PR32658.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300878 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 19:54:02 +00:00
Craig Topper
1fa7ca8b26 [InstCombine] Remove redundant code from SimplifyDemandedBits handling for Or. The code above it is equivalent if you work through the bitwise math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300876 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 19:31:22 +00:00
Paul Robinson
ce35560497 [DWARF] Versioning for DWARF constants; verify FORMs
Associate the version-when-defined with definitions of standard DWARF
constants.  Identify the "vendor" for DWARF extensions.
Use this information to verify FORMs in .debug_abbrev are defined as
of the DWARF version specified in the associated unit.
Removed two tests that had specified DWARF v1 (which essentially does
not exist).

Differential Revision: http://reviews.llvm.org/D30785


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300875 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 19:16:51 +00:00
Chad Rosier
03b48f8380 [AArch64] Improve scheduling of logical operations on Falkor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300871 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 18:50:21 +00:00
Weiming Zhao
a90b36e98b [Thumb-1] Fix corner cases for compressed jump tables
Summary:
When synthesized TBB/TBH is expanded, we need to avoid the case of:
   BaseReg is redefined after the load of branching target. E.g.:

    %R2 = tLEApcrelJT <jt#1>
    %R1 =  tLDRr %R1, %R2    ==> %R2 = tLEApcrelJT <jt#1>
    %R2 = tLDRspi %SP, 12        %R2 = tLDRspi %SP, 12
    tBR_JTr %R1                  tTBB_JT %R2, %R1
`
Reviewers: jmolloy

Reviewed By: jmolloy

Subscribers: llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D32250

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300870 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 18:37:14 +00:00
Davide Italiano
b2a1e2499a [CodeExtractor] Remove a bunch of unneeded constructors.
Differential Revision:  https://reviews.llvm.org/D32305

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300869 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-20 18:33:40 +00:00