14578 Commits

Author SHA1 Message Date
Matthias Braun
88d207542b Cleanup dump() functions.
We had various variants of defining dump() functions in LLVM. Normalize
them (this should just consistently implement the things discussed in
http://lists.llvm.org/pipermail/cfe-dev/2014-January/034323.html

For reference:
- Public headers should just declare the dump() method but not use
  LLVM_DUMP_METHOD or #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
- The definition of a dump method should look like this:
  #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
  LLVM_DUMP_METHOD void MyClass::dump() {
    // print stuff to dbgs()...
  }
  #endif

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293359 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-28 02:02:38 +00:00
Chris Ray
8a25ec8fd0 [X86] Adding FFREEP instruction.
Summary: Small change to get the FREEP instruction to decode properly.

Reviewers: craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29193

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293314 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-27 18:02:53 +00:00
Simon Pilgrim
10559c6633 [X86][SSE] Add support for combining ANDNP byte masks with target shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293178 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-26 14:31:12 +00:00
Simon Pilgrim
b81877488f [X86][SSE] Pull out target shuffle resolve code into helper. NFCI.
Pulled out code that removed unused inputs from a target shuffle mask into a helper function to allow it to be reused in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293175 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-26 13:06:02 +00:00
Craig Topper
facc9962a6 [AVX-512] Move the combine that runs combineBitcastForMaskedOp to the last DAG combine phase where I had originally meant to put it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293157 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-26 07:17:58 +00:00
Craig Topper
3cd2419e8b [X86] When bitcasting INSERT_SUBVECTOR/EXTRACT_SUBVECTOR to match masked operations, use the correct type for the immediate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293156 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-26 07:17:53 +00:00
Jonas Paulsson
7cb6abb7cb [TargetTransformInfo] Refactor and improve getScalarizationOverhead()
Refactoring to remove duplications of this method.

New method getOperandsScalarizationOverhead() that looks at the present unique
operands and add extract costs for them. Old behaviour was to just add extract
costs for one operand of the type always, which still happens in
getArithmeticInstrCost() if no operands are provided by the caller.

This is a good start of improving on this, but there are more places
that can be improved by using getOperandsScalarizationOverhead().

Review: Hal Finkel
https://reviews.llvm.org/D29017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293155 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-26 07:03:25 +00:00
Mohammed Agabaria
e0bafdf059 [X86] enable memory interleaving for X86\SLM arch.
Differential Revision: https://reviews.llvm.org/D28547


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293040 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-25 09:14:48 +00:00
Coby Tayree
4cfd2ebb6d [X86]Enable the use of 'mov' with a 64bit GPR and a large immediate
Enable the next form (intel style):
"mov <reg64>, <largeImm>"
which is should be available,
where <largeImm> stands for immediates which exceed the range of a singed 32bit integer

Differential Revision: https://reviews.llvm.org/D28988



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293030 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-25 07:09:42 +00:00
Simon Pilgrim
74df25e831 [X86][AVX512] Remove unused argument from PMOVX tablegen patterns. NFCI.
Seems to be a copy+paste legacy from the AVX2 patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292941 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 16:16:29 +00:00
Martin Bohme
a441aef21c [X86][SSE] Add explicit braces to avoid -Wdangling-else warning.
Reviewers: RKSimon

Subscribers: llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D29076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292924 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 12:31:30 +00:00
Simon Pilgrim
930bc2d28b Fix unused variable warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292921 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 11:54:27 +00:00
Simon Pilgrim
b9c01fbcf7 [X86][SSE] Add support for constant folding vector arithmetic shift by immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292919 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 11:46:13 +00:00
Simon Pilgrim
9334970101 [X86][SSE] Add support for constant folding vector logical shift by immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292915 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 11:21:57 +00:00
Craig Topper
f2b977986b [X86] Remove unnecessary peakThroughBitcasts call that's already take care of by the ISD::isBuildVectorAllOnes check below.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292894 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 06:57:29 +00:00
Craig Topper
470940f6ef [AVX-512] Simplify multiclasses for integer logic operations. There were several inputs that didn't vary.
While there give them the same scheduling itinerary as the SSE/AVX versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292892 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 06:25:34 +00:00
Craig Topper
a461826967 [X86] Don't split v8i32 all ones values if only AVX1 is available. Keep it intact and split it at isel.
This allows us to remove the check in ANDN combining that had to look through the extraction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292881 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 04:33:03 +00:00
Craig Topper
c144a2489f [X86] Remove Undef handling from extractSubVector. This is now handled inside getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292877 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 02:43:54 +00:00
Simon Pilgrim
f9440ffb06 [X86][SSE] Add missing X86ISD::ANDNP combines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292767 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-22 22:45:23 +00:00
Simon Pilgrim
160800e73a [X86][SSE] Improve shuffle combining with zero insertions
Add support for handling shuffles with scalar_to_vector(0)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292766 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-22 22:21:44 +00:00
Sanjay Patel
873d460b05 [x86] avoid crashing with illegal vector type (PR31672)
https://llvm.org/bugs/show_bug.cgi?id=31672


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292758 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-22 17:06:12 +00:00
Craig Topper
932a081385 [X86] Don't allow commuting to form phsub operations.
Fixes PR31714.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292713 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-21 06:59:38 +00:00
Simon Pilgrim
888319b41c Remove trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292613 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-20 15:15:59 +00:00
Simon Pilgrim
28ad0fea24 [CostModel][X86] Removed unused cost. NFCI.
SHL v8i32 is already handled in the SSE41 cost table

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292612 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-20 15:14:38 +00:00
Simon Pilgrim
38e046e872 [X86][SSE] Improve comments describing combineTruncatedArithmetic. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292502 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19 18:18:32 +00:00
Simon Pilgrim
2d628eed7f [X86][SSE] Attempt to pre-truncate arithmetic operations that have already been extended
As discussed on D28219 - it is profitable to combine trunc(binop (s/zext(x), s/zext(y)) to binop(trunc(s/zext(x)), trunc(s/zext(y))) assuming the trunc(ext()) will simplify further

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292493 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19 16:25:02 +00:00
Elena Demikhovsky
f7484a051a Recommiting unsigned saturation with a bugfix.
A test case that crached is added to avx512-trunc.ll.
(PR31589)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292479 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19 12:08:21 +00:00
Craig Topper
f1fe387ada [AVX-512] Support ADD/SUB/MUL of mask vectors
Summary:
Currently we expand and scalarize these operations, but I think we should be able to implement ADD/SUB with KXOR and MUL with KAND.

We already do this for scalar i1 operations so I just extended it to vectors of i1.

Reviewers: zvi, delena

Reviewed By: delena

Subscribers: guyblank, llvm-commits

Differential Revision: https://reviews.llvm.org/D28888

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292474 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19 07:12:35 +00:00
Craig Topper
e8138e6346 [X86] Merge LowerADD and LowerSUB into a single LowerADD_SUB since they are identical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292469 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19 03:49:29 +00:00
Craig Topper
2a42c3b9a1 [AVX-512] Use VSHUF instructions instead of two inserts as fallback for subvector broadcasts that can't fold the load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292466 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19 02:34:29 +00:00
Michael Kuperstein
57f0668781 Revert r291670 because it introduces a crash.
r291670 doesn't crash on the original testcase from PR31589,
but it crashes on a slightly more complex one.

PR31589 has the new reproducer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292444 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18 23:05:58 +00:00
Kirill Bobyrev
1dd9f80902 Revert 292404 due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292407 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18 16:34:25 +00:00
Kirill Bobyrev
80480bf6ea [X86] Minor code cleanup to fix several clang-tidy warnings. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292404 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18 16:15:47 +00:00
Michael Zuckerman
476a6c5119 [X86] Improve mul combine for negative multiplayer (2^c - 1)
This patch improves the mul instruction combine function (combineMul) 
by adding new layer of logic. 
In this patch, we are adding the ability to fold (mul x, -((1 << c) -1)) 
or (mul x, -((1 << c) +1)) into (neg(X << c) -x) or (neg((x << c) + x) respective.

Differential Revision: https://reviews.llvm.org/D28232


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292358 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18 09:31:13 +00:00
Marina Yatsina
be4bc8908b [X86] Fix for bugzilla 31576 - add support for "data32" instruction prefix
This patch fixes bugzilla 31576 (https://llvm.org/bugs/show_bug.cgi?id=31576).

"data32" instruction prefix was not defined in the llvm.
An exception had to be added to the X86 tablegen and AsmPrinter because both "data16" and "data32" are encoded to 0x66 (but in different modes).

Differential Revision: https://reviews.llvm.org/D28468



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292352 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18 08:07:51 +00:00
Joerg Sonnenberger
a7862537ba Remove an overeager assert from r288844.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292244 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-17 19:29:15 +00:00
Bob Wilson
aedf6684c8 Revert r291640 change to fold X86 comparison with atomic_load_add.
Even with the fix from r291630, this still causes problems. I get
widespread assertion failures in the Swift runtime's WeakRefCount::increment()
function. I sent a reduced testcase in reply to the commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292242 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-17 19:18:57 +00:00
Craig Topper
1b1ce6ef87 [AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292201 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-17 06:49:59 +00:00
Craig Topper
f031545412 [X86] Merge the disassemblers handling of the different TYPE_RELs by getting the size information from the ENCODING field. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292096 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16 06:49:09 +00:00
Craig Topper
14d16cc514 [X86] Reduce the number of operand 'types' the disassembler needs to deal with. NFCI
We were frequently checking for a list of types and the different types
conveyed no real information. So lump them together explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292095 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16 06:49:03 +00:00
Craig Topper
d925138fc6 [AVX-512] Teach the disassembler about all of the EVEX gather and scatter instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292094 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16 05:44:33 +00:00
Craig Topper
75deb64c6f [AVX-512] Begin giving the disassembler a way to recognize that VSIB is a different encoding than regular addressing modes.
This part first teaches it not to check error if EVEX.V2 is used by a VSIB instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292093 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16 05:44:25 +00:00
Craig Topper
00915333a9 [AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQD
with ZMM index. Similar for SCATTER and the prefetch gather and scatter
instructions.

Fixes PR31618.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292088 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16 00:55:58 +00:00
Craig Topper
ef07090bdf [AVX-512] Fix register class in one of the gather/scatter memory operands so that all 32 bit registers can be allowed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292087 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16 00:55:50 +00:00
Simon Pilgrim
0016b62b09 [CostModel][X86] Fix AVX512BW vector shift costs for vXi16 types
We already have patterns in place to support 128/256-bit shifts without AVX512VL

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292077 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-15 20:44:00 +00:00
Michael Zuckerman
50520f329a Fix blend mask by switch the side of the operand since Blend node uses opposite mask then Select NODE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292066 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-15 16:43:14 +00:00
Craig Topper
af2151d394 [AVX-512] Remove unnecessary duplicate broadcast patterns. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292053 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-15 06:15:45 +00:00
Craig Topper
6a84b24687 [AVX-512] Replicate some broadcast patterns to VLX and disable the AVX2 patterns when VLX is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292051 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-15 05:47:45 +00:00
Craig Topper
ba330b6646 [X86] Remove untested MOVDDUP patterns.
These all involve bitcasts around the memory operands. This isn't
something we normally do for isel patterns. I suspect DAG combine should
convert the load type making this unnecessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292050 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-15 05:21:29 +00:00
Simon Pilgrim
75f614f4c2 [CostModel][X86] Updated vXi64 ASHR costs on AVX512 targets now that D28604 has landed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292023 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-14 19:24:23 +00:00