85 Commits

Author SHA1 Message Date
Michael Zuckerman
c2d5ba110d [AVX512] adding AVXVBMI feature flag
Fixing wrong typo (avx515) → (avx512) 
Review over the shoulder by asaf . 

Differential Revision: http://reviews.llvm.org/D16190


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258041 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-18 11:12:47 +00:00
Michael Zuckerman
d26cdd00ea [AVX512] adding AVXVBMI feature flag
The feature flag is for VPERMB,VPERMI2B,VPERMT2B and VPMULTISHIFTQB instructions. 
More about the instruction can be found in:
hattps://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf

Differential Revision: http://reviews.llvm.org/D16190


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258012 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-17 13:42:12 +00:00
Asaf Badouh
22bb8f5964 [x86] adding PKU feature flag
the feature flag is essential for RDPKRU and WRPKRU instruction 
more about the instruction can be found in the SDM rev 56, vol 2 from http://www.intel.com/sdm

Differential Revision: http://reviews.llvm.org/D15491



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255644 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-15 13:35:29 +00:00
Craig Topper
01e582a1d1 [X86] Update CPU detection to only enable XSAVE features if the OS has enabled them and the saving of YMM state. This seems to be consistent with gcc behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250269 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-14 05:37:42 +00:00
Amjad Aboud
8e03ab46f2 [X86] Add XSAVE intrinsic family
Add intrinsics for the
  XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64)
  XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64)
  XSAVEC instructions (XSAVEC/XSAVEC64)
  XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64)

Differential Revision: http://reviews.llvm.org/D13012

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250029 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-12 11:47:46 +00:00
Chandler Carruth
6aaf0a68ac [ADT] Switch a bunch of places in LLVM that were doing single-character
splits to actually use the single character split routine which does
less work, and in a debug build is *substantially* faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247245 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10 06:12:31 +00:00
Craig Topper
9f7761b487 Add model numbers for Skylake CPUs and an additional Broadwell model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244385 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-08 01:29:15 +00:00
Craig Topper
87432f3518 Add Intel family 6 model 93 as Silvermont.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244384 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-08 01:16:05 +00:00
Craig Topper
9f316a2e0c Add Intel family 6 model 90 as Silvermont. Fixes PR24392.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244352 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-07 20:09:42 +00:00
Ulrich Weigand
1a21909e98 [SystemZ] Add z13 vector facility and MC support
This patch adds support for the z13 processor type and its vector facility,
and adds MC support for all new instructions provided by that facilily.

Apart from defining the new instructions, the main changes are:

- Adding VR128, VR64 and VR32 register classes.
- Making FP64 a subclass of VR64 and FP32 a subclass of VR32.
- Adding a D(V,B) addressing mode for scatter/gather operations
- Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields.
  Until now all immediate operands have been the same width as the
  underlying field (hence the assert->return change in decode[SU]ImmOperand).

In addition, sys::getHostCPUName is extended to detect running natively
on a z13 machine.

Based on a patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:23:40 +00:00
Craig Topper
cd83d5b507 [X86] Stop changing result of getHostCPUName based on whether the processor supports AVX. getHostCPUFeatures should be used instead to determine whether to support AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233674 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 06:18:31 +00:00
Craig Topper
caa12e0352 [X86] Be more robust against unknown Intel family 6 models. Use feature flags to guess what it might be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233671 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 05:42:45 +00:00
Craig Topper
8b042883dc [X86] In getHostCPUFeatures, disable xop, f16c, fma, and fma4 if OS does not support saving ymm state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233518 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 06:31:14 +00:00
Craig Topper
c637444fed [X86] Use the more specific CPU names like 'nehalem', 'westmere', 'haswell', etc. Split Nehalem and Westmere CPUs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233516 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 06:31:09 +00:00
Craig Topper
44f1dccd64 [X86] Move family 6 model 21 to 'pentium-m'. Near as I can tell this is a Dothan based SOC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233515 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 06:31:06 +00:00
Craig Topper
e82327a6ab [X86] Family 6 model 29 is a Penryn based processor not a Nehalem based processor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233514 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-30 06:31:03 +00:00
Craig Topper
f46232d70d Fix a variable name in MSVC specific part of rr233487.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233488 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-29 01:07:57 +00:00
Craig Topper
87f3799e56 [X86] Implement getHostCPUFeatures for X86.
Plan to use this as part of CPU 'native' support so we can stop picking a different CPU name if CPU doesn't support AVX or AVX2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233487 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-29 01:00:23 +00:00
Craig Topper
38d5f48397 Fix typo 'AVX too' instead of 'AVX2'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232929 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23 04:17:11 +00:00
Craig Topper
da740f1e8e [X86] Add one stepping of Broadwell to the CPU name autodetection for march=native.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232927 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23 00:15:06 +00:00
Aaron Ballman
502401111b We require MSVC 1800 as our minimum, so these checks can safely go away; NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229415 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-16 18:23:00 +00:00
Rafael Espindola
650708838d Remove a debugging assert.
Sorry for the noise, I have no idea how it survived to the final version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224414 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 03:38:04 +00:00
Rafael Espindola
9a845bdcd5 Fix the windows build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224412 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 02:42:20 +00:00
Rafael Espindola
2f569017cb Refactor and simplify the code reading /proc/cpuinfo. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224410 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-17 02:32:44 +00:00
David Blaikie
1d4f28c6bc Remove StringMap::GetOrCreateValue in favor of StringMap::insert
Having two ways to do this doesn't seem terribly helpful and
consistently using the insert version (which we already has) seems like
it'll make the code easier to understand to anyone working with standard
data structures. (I also updated many references to the Entry's
key and value to use first() and second instead of getKey{Data,Length,}
and get/setValue - for similar consistency)

Also removes the GetOrCreateValue functions so there's less surface area
to StringMap to fix/improve/change/accommodate move semantics, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222319 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 05:49:42 +00:00
Will Schmidt
842549dfa6 Add support for ppc64/power8 as a host
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211781 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-26 13:37:03 +00:00
Hans Wennborg
caa2bd600c Fix .cpp files claiming to be header files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211334 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-20 01:36:00 +00:00
Alp Toker
4a0555250d Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209982 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-31 21:26:28 +00:00
Bradley Smith
fa16c880f2 Fixup sys::getHostCPUFeatures crypto names so it doesn't clash with kernel headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209506 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-23 10:14:13 +00:00
Bradley Smith
00011c71f9 Extend sys::getHostCPUFeatures to work on AArch64 platforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209420 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:44:34 +00:00
Kaelyn Takata
54d2b33222 Select bdver2 instead of bdver1 if TBM support is present on models < 0x10.
Tested that the right -target-cpu is set in the clang -cc1 command line
when running "clang -march=native -E -v - </dev/null" on both an FX-8150
and an FX-8350. Both are family 15h; the FX-8150 (Bulldozer processor)
reports a model number of 1, and the FX-8350 (Piledriver processor)
reports a model number of 2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207973 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 16:32:10 +00:00
Benjamin Kramer
3cddd1607c Add a description for AMD's bdver4 (aka Excavator).
This is just bdver3 + AVX2 + BMI2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207847 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-02 15:47:07 +00:00
Chandler Carruth
bb67355af8 [Modules] Followup to r206822 to add a DEBUG_TYPE which is used on ARM
and PPC, but not x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206830 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 23:58:10 +00:00
Kai Nacke
66732aeff2 Add support for krait cpu in llvm::sys::getHostCPUName()
Recently, support for krait cpu was added. This commit extends getHostCPUName()
to return krait as cpu for the APQ8064 (a Krait 300).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-20 09:24:13 +00:00
Rafael Espindola
35e19348d9 Fix Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197168 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-12 16:17:40 +00:00
Rafael Espindola
e60ffe35a2 Convert the other getHostByName implementations to StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-12 16:10:48 +00:00
Rafael Espindola
9191be9523 Return a StringRef from getHostCPUName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197158 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-12 15:45:32 +00:00
Benjamin Kramer
1b4c8c1fc8 Make helper function static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195650 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-25 15:40:24 +00:00
Tim Northover
8a6c627fd0 X86: enable AVX2 under Haswell native compilation
Patch by Adam Strzelecki

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195632 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-25 09:52:59 +00:00
Benjamin Kramer
00e3be6134 X86: Add a description for AMD bdver3 aka Steamroller.
This is just bdver2 + FSGSBase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 10:29:20 +00:00
Richard Sandiford
793ce99ea7 [SystemZ] Automatically detect zEC12 and z196 hosts
As on other hosts, the CPU identification instruction is priveleged,
so we need to look through /proc/cpuinfo.  I copied the PowerPC way of
handling "generic".

Several tests were implicitly assuming z10 and so failed on z196.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 12:14:17 +00:00
Preston Gurd
94dc6540a8 Adds support for Atom Silvermont (SLM) - -march=slm
Implements Instruction scheduler latencies for Silvermont,
using latencies from the Intel Silvermont Optimization Guide.

Auto detects SLM.

Turns on post RA scheduler when generating code for SLM.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-13 19:23:28 +00:00
Benjamin Kramer
d7a178eee3 X86: Add a description of the Intel Atom Silvermont CPU.
Currently this is just the atom model with SSE4.2 enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189669 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-30 14:05:32 +00:00
Reid Kleckner
0c1c5b0aaa Actually, use GNU inline asm for cpuid with clang
Clang doesn't support the MSVC __cpuid intrinsic yet, and fixing that is
blocked on some fairly complicated issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188584 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 22:42:42 +00:00
Reid Kleckner
c97db8dfdd Use the MSVC __cpuid intrinsic instead of inline asm
This works around PR16830 in LLVM when self-hosting clang on Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 18:21:51 +00:00
Benjamin Kramer
9e036910f8 Some Intel Penryn CPUs come with SSE4 disabled. Detect them as core 2.
PR16721.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187350 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-29 11:02:08 +00:00
Duncan Sands
e8a2742352 Ensure sys::getProcessTriple always uses a normalized triple. Patch by
Thomas B. Jablin, from PR16636.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-17 11:01:05 +00:00
Tobias Grosser
a85644459c Make host ARM CPU feature detection independent of the vendor
For ARM on linux we use /proc/cpuinfo to detect the host CPU's features.
Linux derives these values without ever looking at the vendor of the
specific CPU implementation. Hence, it adds little value, if we parse
the output of /proc/cpuinfo only for certain vendors.

This patch enables us to derive the correct feature flags e.g. for Qualcomm
CPUs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 21:45:01 +00:00
Tim Northover
d66ad6c571 Allow host triple to be correctly overridden in CMake builds
The intended semantics mirror autoconf, where the user is able to
specify a host triple, but if it's left to the build system then
"config.guess" is invoked for the default.

This also renames the LLVM_HOSTTRIPLE define to LLVM_HOST_TRIPLE to
fit in with the style of the surrounding defines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 07:36:23 +00:00
Benjamin Kramer
b9548d8ee3 X86: Add target description for btver2; make autodetection logic aware of AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 10:20:08 +00:00