10 Commits

Author SHA1 Message Date
Matthias Braun
db9ce2fda6 MachineFunction: Introduce NoPHIs property
I want to compute the SSA property of .mir files automatically in
upcoming patches. The problem with this is that some inputs will be
reported as static single assignment with some passes claiming not to
support SSA form.  In reality though those passes do not support PHI
instructions => Track the presence of PHI instructions separate from the
SSA property.

Differential Revision: https://reviews.llvm.org/D22719

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279573 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-23 21:19:49 +00:00
Hans Wennborg
46b81ba7eb Fix more dereferenced end() iterators after r278532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278587 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-13 01:12:49 +00:00
Matt Arsenault
dca409d5ad AMDGPU: Move subtarget feature checks into passes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273937 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-27 20:32:13 +00:00
Matt Arsenault
759ed7e410 AMDGPU: Cleanup subtarget handling.
Split AMDGPUSubtarget into amdgcn/r600 specific subclasses.
This removes most of the static_casting of the basic codegen
classes everywhere, and tries to restrict the features
visible on the wrong target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273652 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-24 06:30:11 +00:00
Rafael Espindola
1963865e9d Delete some dead code.
Found by gcc 6.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273303 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-21 19:48:12 +00:00
Andrew Kaylor
c7ca1302cf Add optimization bisect opt-in calls for AMDGPU passes
Differential Revision: http://reviews.llvm.org/D19450



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267485 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-25 22:23:44 +00:00
Konstantin Zhuravlyov
338aaed82f Test commit access
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264736 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-29 15:15:44 +00:00
Duncan P. N. Exon Smith
42e18357c5 CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC
Take MachineInstr by reference instead of by pointer in SlotIndexes and
the SlotIndex wrappers in LiveIntervals.  The MachineInstrs here are
never null, so this cleans up the API a bit.  It also incidentally
removes a few implicit conversions from MachineInstrBundleIterator to
MachineInstr* (see PR26753).

At a couple of call sites it was convenient to convert to a range-based
for loop over MachineBasicBlock::instr_begin/instr_end, so I added
MachineBasicBlock::instrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262115 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-27 06:40:41 +00:00
Matt Arsenault
3aa0d7cb53 AMDGPU/SI: Fix read2 merging into a super register.
If the read2 produced was supposed to be writing into a
super register, it would use the wrong subregister indices.
Fix this by inserting copies, so we only ever write to a vreg_64.
Run the register coalescer again to clean this up, although this
isn't ideal and often does result in an extra move.

Also remove the assert that offset1 > offset0.

There isn't a real reason to not allow this other than a minor
convenience in the compiler, and it doesn't seem worth the effort
of avoiding it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242174 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-14 17:57:36 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00