Commit Graph

149104 Commits

Author SHA1 Message Date
Peter Collingbourne
851b7e5dc8 FunctionImport: Simplify function llvm::thinLTOInternalizeModule. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302595 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 22:43:31 +00:00
Lang Hames
ab3dba86f9 [ExecutionEngine] Make RuntimeDyld::MemoryManager responsible for tracking EH
frames.

RuntimeDyld was previously responsible for tracking allocated EH frames, but it
makes more sense to have the RuntimeDyld::MemoryManager track them (since the
frames are allocated through the memory manager, and written to memory owned by
the memory manager). This patch moves the frame tracking into
RTDyldMemoryManager, and changes the deregisterFrames method on
RuntimeDyld::MemoryManager from:

void deregisterEHFrames(uint8_t *Addr, uint64_t LoadAddr, size_t Size);

to:

void deregisterEHFrames();

Separating this responsibility will allow ORC to continue to throw the
RuntimeDyld instances away post-link (saving a few dozen bytes per lazy
function) while properly deregistering frames when modules are unloaded.

This patch also updates ORC to call deregisterEHFrames when modules are
unloaded. This fixes a bug where an exception that tears down the JIT can then
unwind through dangling EH frames that have been deallocated but not
deregistered, resulting in UB.

For people using SectionMemoryManager this should be pretty much a no-op. For
people with custom allocators that override registerEHFrames/deregisterEHFrames,
you will now be responsible for tracking allocated EH frames.

Reviewed in https://reviews.llvm.org/D32829



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302589 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 21:32:18 +00:00
Keno Fischer
54fd142e36 [GVN] Fix a crash on encountering non-integral pointers
Summary:
This fixes the immediate crash caused by introducing an incorrect inttoptr
before attempting the conversion. There may still be a legality
check missing somewhere earlier for non-integral pointers, but this change
seems necessary in any case.

Reviewers: sanjoy, dberlin

Reviewed By: dberlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32623

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302587 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 21:07:20 +00:00
Stanislav Mekhanoshin
f7e315844f [AMDGPU] Fixed typo in GCNRegPressure, NFC
VGRP -> VGPR, SGRP -> SGPR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302586 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 20:50:04 +00:00
Sanjay Patel
f90dff1344 [InstCombine] update test file to use FileCheck; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302585 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 20:46:12 +00:00
Zvi Rackover
14cb3039db DAGCombine: Combine shuffles of splat-shuffles
Summary: Reapply r299047, but this time handle correctly splat-masks with undef elements.

Reviewers: spatel, RKSimon, eli.friedman, andreadb

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31961

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302583 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 20:25:38 +00:00
Matthew Simpson
a4fa9d3a63 [AArch64] Consider widening instructions in cost calculations
The AArch64 instruction set has a few "widening" instructions (e.g., uaddl,
saddl, uaddw, etc.) that take one or more doubleword operands and produce
quadword results. The operands are automatically sign- or zero-extended as
appropriate. However, in LLVM IR, these extends are explicit. This patch
updates TTI to consider these widening instructions as single operations whose
cost is attached to the arithmetic instruction. It marks extends that are part
of a widening operation "free" and applies a sub-target specified overhead
(zero by default) to the arithmetic instructions.

Differential Revision: https://reviews.llvm.org/D32706

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302582 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 20:18:12 +00:00
Sanjay Patel
cf5da38c84 [InstCombine] clean up matchDeMorgansLaws(); NFCI
The motivation for getting rid of dyn_castNotVal is to allow fixing:
https://bugs.llvm.org/show_bug.cgi?id=32706

So this was supposed to be functional-change-intended for the case
of inverting constants and applying DeMorgan. However, I can't find 
any cases where that pattern will actually get to matchDeMorgansLaws()
because we have other folds in visitAnd/visitOr that do the same
thing. So this ends up just being a clean-up patch with slight efficiency
improvement, but no-functional-change-intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302581 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 20:05:05 +00:00
Davide Italiano
bcfd2ccde0 [NewGVN] Simplify a DEBUG() statement. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302579 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 20:02:48 +00:00
Reid Kleckner
e32aebf279 [codeview] Check for a DIExpression offset for local variables
Fixes inalloca parameters, which previously all pointed to the same
offset. Extend the test to use llvm-readobj so that we can test the
offset in a readable way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302578 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 19:59:29 +00:00
Adrian Prantl
8b2dee8975 Make it illegal for two Functions to point to the same DISubprogram
As recently discussed on llvm-dev [1], this patch makes it illegal for
two Functions to point to the same DISubprogram and updates
FunctionCloner to also clone the debug info of a function to conform
to the new requirement. To simplify the implementation it also factors
out the creation of inlineAt locations from the Inliner into a
general-purpose utility in DILocation.

[1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html
<rdar://problem/31926379>

Differential Revision: https://reviews.llvm.org/D32975

This reapplies r302469 with a fix for a bot failure (reparentDebugInfo
now checks for the case the orig and new function are identical).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302576 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 19:47:37 +00:00
Piotr Padlewski
e6140e7c19 NFC: refactor replaceDominatedUsesWith
Summary:
Since I will post patch with some changes to
replaceDominatedUsesWith, it would be good to avoid
duplicating code again.

Reviewers: davide, dberlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32798

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302575 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 19:39:44 +00:00
Wolfgang Pieb
7cbfb46ab9 [DWARF] Fix a parsing issue with type unit headers.
Reviewers: dblaikie

Differential Revision: https://reviews.llvm.org/D32987


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302574 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 19:38:38 +00:00
Eric Beckmann
ddb4f9c38b Fix the Endianness bug by adding the little endian UTF marker.
Summary: Quick fix

Reviewers: zturner, uweigand

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33014

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302573 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 19:35:45 +00:00
Serge Guelton
d35f86ef8f Suppress all uses of LLVM_END_WITH_NULL. NFC.
Use variadic templates instead of relying on <cstdarg> + sentinel.
This enforces better type checking and makes code more readable.

Differential Revision: https://reviews.llvm.org/D32541


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302571 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 19:31:13 +00:00
Jacques Pienaar
ddeab36df7 [lanai] Add computeKnownBitsForTargetNode for Lanai.
Summary: computeKnownBitsForTargetNode was not defined for Lanai which resulted in additional AND's with 0x1 for the output of SETCC instructions.

Reviewers: eliben, majnemer

Reviewed By: majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29605

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302568 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 18:35:26 +00:00
Davide Italiano
d65047601c [NewGVN] Explain why sorting by pointer values doesn't introduce non-determinism.
Thanks to Eli for pointing out in a post-commit review comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302566 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 18:29:37 +00:00
Ulrich Weigand
5600d46a6d [SystemZ] Support missing relocation types in RuntimeDyldELF
Handle some more relocation types in
RuntimeDyldELF::resolveSystemZRelocation

This fixes a number of failing LLDB test cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302565 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 18:27:39 +00:00
Sam Clegg
072e32f089 [WebAssembly] Fix validation of start function
The check for valid start function was inverted.  Added a new
test in test/Object to check this case and fixed the existing
tests in for ObjectYAML.

Differential Revision: https://reviews.llvm.org/D32986

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302560 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 17:51:38 +00:00
Krzysztof Parzyszek
8a634a8824 [RegScavenger] Rangify a loop, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302554 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 17:16:52 +00:00
Puyan Lotfi
92fa36802d Adding VSCode syntax colorizer to utils (generated from textmate colorizer).
--This line, and those below, will be igored--

A    utils/vscode
A    utils/vscode/README
A    utils/vscode/tablegen
A    utils/vscode/tablegen/.vscode
A    utils/vscode/tablegen/.vscode/launch.json
A    utils/vscode/tablegen/CHANGELOG.md
A    utils/vscode/tablegen/README.md
A    utils/vscode/tablegen/language-configuration.json
A    utils/vscode/tablegen/package.json
A    utils/vscode/tablegen/syntaxes
A    utils/vscode/tablegen/syntaxes/TableGen.tmLanguage
A    utils/vscode/tablegen/vsc-extension-quickstart.md


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302553 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 17:13:37 +00:00
Davide Italiano
9689ee1fa3 [NewGVN] Fix a consistent order for phi nodes operands.
The way we currently define congruency for two PHIExpression(s) is:

1) The operands to the phi functions are congruent
2) The PHIs are defined in the same BasicBlock.

NewGVN works under the assumption that phi operands are in predecessor
order, or at least in some consistent order. OTOH, is valid IR:

patatino:
  %meh = phi i16 [ %0, %winky ], [ %conv1, %tinky ]
  %banana = phi i16 [ %0, %tinky ], [ %conv1, %winky ]
  br label %end

and the in-memory representations of the two SSA registers have an
inconsistent order. This violation of NewGVN assumptions results into
two PHIs found congruent when they're not. While we think it's useful
to have always a consistent order enforced, let's fix this in NewGVN
sorting uses in predecessor order before creating a PHI expression.

Differential Revision:  https://reviews.llvm.org/D32990

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302552 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:58:28 +00:00
Craig Topper
80f6556e8a [APInt] Remove return value from tcFullMultiply.
The description says it returns the number of words needed to represent the results. But the way it was coded it always returns (lhsWords + rhsWords) or (lhsWords + rhsWords - 1). But the result could be even smaller than that and it wouldn't tell you.

No one uses the result today so rather than try to fix it, just remove it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302551 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:47:33 +00:00
Daniel Berlin
954e86756a NewGVN: Make all of symbolic evaluation logically const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302550 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:40:04 +00:00
Craig Topper
0e5156e98f [X86] Add more patterns for BZHI isel
This patch adds more patterns that a reasonable person might write that can be compiled to BZHI.

This adds support for

(~0U >> (32 - b)) & a;

and

a << (32 - b) >> (32 - b);

This was inspired by the code in APInt::clearUnusedBits.

This can pass an index of 32 to the bzhi instruction which a quick test of Haswell hardware shows will not mask any bits. Though the description text in the Intel manual says the "index is saturated to OperandSize-1". The pseudocode in the same manual indicates no bits will be zeroed for this case.

I think this is still missing cases where the subtract portion is an 8-bit operation.

Differential Revision: https://reviews.llvm.org/D32616

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302549 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:32:11 +00:00
Sanjay Patel
5c355ea7dc [InstCombineCasts] Fix checks in sext->lshr->trunc pattern.
The comment says to avoid the case where zero bits are shifted into the truncated value, 
but the code checks that the shift is smaller than the truncated value instead of the 
number of bits added by the sign extension. Fixing this allows a shift by more than the 
value size to be introduced, which is undefined behavior, so the shift is capped at the 
value size minus one, which has the expected behavior of filling the value with the sign 
bit.

Patch by Jacob Young!

Differential Revision: https://reviews.llvm.org/D32285



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302548 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:24:59 +00:00
Guy Blank
a610a6eaf3 VX512] Only look at lower bit in constant scalar masks
for scalar masked instructions only the lower bit of the mask is relevant. so for constant masks we should either do an unmasked operation or no operation, depending on the value of the lower bit.
This patch handles cases where the lower bit is '1'.

Differential Revision: https://reviews.llvm.org/D32805

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302546 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:16:48 +00:00
Reid Kleckner
7dfa173654 Re-land "Use the frame index side table for byval and inalloca arguments"
This re-lands r302483. It was not the cause of PR32977.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302544 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:02:20 +00:00
Reid Kleckner
d3285d0ce4 Re-land "Don't add DBG_VALUE instructions for static allocas in dbg.declare"
This re-lands commit r302461. It was not the cause of PR32977.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302543 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:01:47 +00:00
Tim Shen
f52671da9b [Atomic] Remove IsStore/IsLoad in the interface, and pass the instruction instead. NFC.
Now both emitLeadingFence and emitTrailingFence take the instruction
itself, instead of taking IsLoad/IsStore pairs.
Instruction::mayReadFromMemory and Instrucion::mayWriteToMemory are used
for determining those two booleans.

The instruction argument is also useful for later D32763, in
emitTrailingFence. For emitLeadingFence, it seems to have cleaner
interface with the proposed change.

Differential Revision: https://reviews.llvm.org/D32762

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302539 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 15:27:17 +00:00
Aaron Ballman
25e22520d5 Amend r302535; ifndef and ifdef are different, as it turns out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302537 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 15:12:03 +00:00
Aaron Ballman
dd718cb76d ARMRegisterBankInfo.h requires LLVM_BUILD_GLOBAL_ISEL to be defined. If it is not defined, then ARMGenRegisterBank.inc is not table generated and the inclusion of this header causes the build to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302535 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 14:59:48 +00:00
Hans Wennborg
1f81185df2 Revert r302469 "Make it illegal for two Functions to point to the same DISubprogram"
This caused PR32977.

Original commit message:

> Make it illegal for two Functions to point to the same DISubprogram
>
> As recently discussed on llvm-dev [1], this patch makes it illegal for
> two Functions to point to the same DISubprogram and updates
> FunctionCloner to also clone the debug info of a function to conform
> to the new requirement. To simplify the implementation it also factors
> out the creation of inlineAt locations from the Inliner into a
> general-purpose utility in DILocation.
>
> [1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html
> <rdar://problem/31926379>
>
> Differential Revision: https://reviews.llvm.org/D32975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302533 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 14:44:15 +00:00
Anna Thomas
1fbed43c3e [LV] Fix insertion point for shuffle vectors in first order recurrence
Summary:
In first order recurrence vectorization, when the previous value is a phi node, we need to
set the insertion point to the first non-phi node.
We can have the previous value being a phi node, due to the generation of new
IVs as part of trunc optimization [1].

[1] https://reviews.llvm.org/rL294967

Reviewers: mssimpso, mkuper

Subscribers: mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D32969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302532 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 14:29:33 +00:00
Aaron Ballman
9bd179193e Removing a file that is not necessary (and was causing link diagnostics with MSVC 2015); NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302531 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 14:22:48 +00:00
Guy Blank
a26ddccfa2 [X86][AVX512] Refine some avx512er intrinsics tests. NFC.
The modified tests should test the masked intrinsics.
Currently the mask is constant, which with a future patch (https://reviews.llvm.org/D32805) will cause the intrinsics to be replaced with an unmasked version.
This patch changes the constant mask to be a variable one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302529 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 14:03:51 +00:00
Serge Pavlov
1f4a80fdc1 Add extra operand to CALLSEQ_START to keep frame part set up previously
Using arguments with attribute inalloca creates problems for verification
of machine representation. This attribute instructs the backend that the
argument is prepared in stack prior to  CALLSEQ_START..CALLSEQ_END
sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size
stored in CALLSEQ_START in this case does not count the size of this
argument. However CALLSEQ_END still keeps total frame size, as caller can
be responsible for cleanup of entire frame. So CALLSEQ_START and
CALLSEQ_END keep different frame size and the difference is treated by
MachineVerifier as stack error. Currently there is no way to distinguish
this case from actual errors.

This patch adds additional argument to CALLSEQ_START and its
target-specific counterparts to keep size of stack that is set up prior to
the call frame sequence. This argument allows MachineVerifier to calculate
actual frame size associated with frame setup instruction and correctly
process the case of inalloca arguments.

The changes made by the patch are:
- Frame setup instructions get the second mandatory argument. It
  affects all targets that use frame pseudo instructions and touched many
  files although the changes are uniform.
- Access to frame properties are implemented using special instructions
  rather than calls getOperand(N).getImm(). For X86 and ARM such
  replacement was made previously.
- Changes that reflect appearance of additional argument of frame setup
  instruction. These involve proper instruction initialization and
  methods that access instruction arguments.
- MachineVerifier retrieves frame size using method, which reports sum of
  frame parts initialized inside frame instruction pair and outside it.

The patch implements approach proposed by Quentin Colombet in
https://bugs.llvm.org/show_bug.cgi?id=27481#c1.
It fixes 9 tests failed with machine verifier enabled and listed
in PR27481.

Differential Revision: https://reviews.llvm.org/D32394


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302527 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 13:35:13 +00:00
Simon Dardis
5cd1e6d400 Revert "[MIPS] Add support to match more patterns for DINS instruction"
This reverts commit rL302512. This broke the mips buildbots.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302526 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 13:18:48 +00:00
Simon Pilgrim
d1adb786cc [X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X)
Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD.

Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure. Although it does require a second register, given that this is a (cheap) zero register the impact is minimal.

Differential Revision: https://reviews.llvm.org/D32973

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302525 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 13:14:40 +00:00
Diana Picus
42ab77b051 Revert "[Dwarf] Disable reference verification for now (PR32972)"
This reverts commit r302520 because it break the unit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302524 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 13:05:43 +00:00
Renato Golin
972328b093 [Dwarf] Disable reference verification for now (PR32972)
There is no other explanation about why this only started happening
now, even though it crashes on old code (supposedly reachable from
here).

The only common factor between the failing bots is that they use GCC
(4.9 and 5.3) to compile Clang, while the others use Clang 3.8, but the
failure is while building the tests, as an assertion, on Clang.

Commenting it out for now in hope the bots will go back green, but we
should keep looking for the real cause, and update bugzilla.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302520 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 12:36:50 +00:00
Guy Blank
3997018899 [X86][AVX512] Add test for masking of scalar instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302519 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 12:32:48 +00:00
Amara Emerson
8f1f7ce9d1 Introduce experimental generic intrinsics for horizontal vector reductions.
- This change allows targets to opt-in to using them instead of the log2
  shufflevector algorithm.
- The SLP and Loop vectorizers have the common code to do shuffle reductions
  factored out into LoopUtils, and now have a unified interface for generating
  reductions regardless of the preference of the target. LoopUtils now uses TTI
  to determine what kind of reductions the target wants to handle.
- For CodeGen, basic legalization support is added.

Differential Revision: https://reviews.llvm.org/D30086



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302514 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 10:43:25 +00:00
Nikolai Bozhenov
64dbd2ef25 [X86] Clang option -fuse-init-array has no effect when generating for MCU target
Reviewers: Eugene.Zelenko, dschuff, craig.topper

Reviewed By: craig.topper

Subscribers: ahatanak, aaboud, DavidKreitzer, llvm-commits, cfe-commits

Differential Revision: https://reviews.llvm.org/D32543
Patch by AndreiGrischenko <andrei.l.grischenko@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302513 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 10:14:03 +00:00
Strahinja Petrovic
4ab11e2a6b [MIPS] Add support to match more patterns for DINS instruction
This patch adds support for recognizing patterns to match
DINS instruction.

Differential Revision: https://reviews.llvm.org/D31465


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302512 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 10:02:00 +00:00
Diana Picus
4f0f7c08bf [ARM GlobalISel] Remove hand-written G_FADD selection
Remove the code selecting G_FADD - now that TableGen can handle more
opcodes, it's not needed anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302511 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 08:32:42 +00:00
Craig Topper
b23f8ea900 [ConstantRange] Rewrite shl to avoid repeated calls to getUnsignedMax and avoid creating the min APInt until we're sure we need it. Use inplace shift operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302510 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 07:04:04 +00:00
Craig Topper
eef1c41964 [ConstantRange] Combine the two adds max+1 in lshr into a single addition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302509 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 07:04:02 +00:00
Craig Topper
384ba40c27 [ConstantRange] Use APInt::isNullValue in place of comparing with 0. The compiler should be able to generate slightly better code for the former. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302508 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 05:01:29 +00:00
Reid Kleckner
5c900216f1 Revert "Don't add DBG_VALUE instructions for static allocas in dbg.declare"
This reverts commit r302461.

It appears to be causing failures compiling gtest with debug info on the
Linux sanitizer bot. I was unable to reproduce the failure locally,
however.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302504 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 01:57:44 +00:00