llvm/lib/Target/CellSPU
2009-01-20 19:12:24 +00:00
..
AsmPrinter Add the private linkage. 2009-01-15 20:18:42 +00:00
CellSDKIntrinsics.td
CMakeLists.txt CMake: Reflected changes on the CellSPU target build. May require a 2008-11-08 20:37:19 +00:00
Makefile Removed trailing whitespace from Makefiles. 2009-01-09 16:44:42 +00:00
README.txt CellSPU: Update the README 2009-01-06 03:51:14 +00:00
SPU64InstrInfo.td - Convert remaining i64 custom lowering into custom instruction emission 2009-01-15 04:41:47 +00:00
SPU128InstrInfo.td CellSPU: 2009-01-06 03:36:14 +00:00
SPU.h Tidy up #includes, deleting a bunch of unnecessary #includes. 2009-01-05 17:59:02 +00:00
SPU.td - Start moving target-dependent nodes that could be represented by an 2008-12-30 23:28:25 +00:00
SPUCallingConv.td CellSPU: 2009-01-06 23:10:38 +00:00
SPUFrameInfo.cpp
SPUFrameInfo.h
SPUHazardRecognizers.cpp Generalize the HazardRecognizer interface so that it can be used 2009-01-15 22:18:12 +00:00
SPUHazardRecognizers.h Generalize the HazardRecognizer interface so that it can be used 2009-01-15 22:18:12 +00:00
SPUInstrBuilder.h Fix constant pool loads, and remove broken versions of addConstantPoolReference. 2008-09-06 01:11:01 +00:00
SPUInstrFormats.td - Remove Tilmann's custom truncate lowering: it completely hosed over 2008-12-27 04:51:36 +00:00
SPUInstrInfo.cpp Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 2009-01-20 19:12:24 +00:00
SPUInstrInfo.h Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 2009-01-20 19:12:24 +00:00
SPUInstrInfo.td - Convert remaining i64 custom lowering into custom instruction emission 2009-01-15 04:41:47 +00:00
SPUISelDAGToDAG.cpp Generalize the HazardRecognizer interface so that it can be used 2009-01-15 22:18:12 +00:00
SPUISelLowering.cpp - Convert remaining i64 custom lowering into custom instruction emission 2009-01-15 04:41:47 +00:00
SPUISelLowering.h - Convert remaining i64 custom lowering into custom instruction emission 2009-01-15 04:41:47 +00:00
SPUMachineFunction.h
SPUMathInstr.td - Convert remaining i64 custom lowering into custom instruction emission 2009-01-15 04:41:47 +00:00
SPUNodes.td - Convert remaining i64 custom lowering into custom instruction emission 2009-01-15 04:41:47 +00:00
SPUOperands.td - Remove Tilmann's custom truncate lowering: it completely hosed over 2008-12-27 04:51:36 +00:00
SPURegisterInfo.cpp - Start moving target-dependent nodes that could be represented by an 2008-12-30 23:28:25 +00:00
SPURegisterInfo.h
SPURegisterInfo.td CellSPU: 2009-01-06 23:10:38 +00:00
SPURegisterNames.h
SPUSchedule.td
SPUSubtarget.cpp
SPUSubtarget.h CellSPU: 2009-01-06 23:10:38 +00:00
SPUTargetAsmInfo.cpp - Remove Tilmann's custom truncate lowering: it completely hosed over 2008-12-27 04:51:36 +00:00
SPUTargetAsmInfo.h Teach CellSPU about ELF sections and new section emitter classes. 2008-11-07 04:36:25 +00:00
SPUTargetMachine.cpp CellSPU: 2008-12-10 00:15:19 +00:00
SPUTargetMachine.h CellSPU: 2008-12-10 00:15:19 +00:00

//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//

This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:

- Scott Michel (head bottle washer and much of the non-floating point
  instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)
- Nehal Desai (debugging, RoadRunner SPU expertise)

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE.

---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:

If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:

        ./configure <your_configure_flags_here> \
           --enable-targets=x86,x86_64,powerpc,spu

---------------------------------------------------------------------------

TODO:
* Create a machine pass for performing dual-pipeline scheduling specifically
  for CellSPU, handle inserting branch prediction instructions.

* i32 instructions:

  * i32 division (work-in-progress)

* i64 support (see i64operations.c test harness):

  * shifts and comparison operators: done
  * sign and zero extension: done
  * addition: done
  * subtraction: needed
  * multiplication: work-in-progress

* i128 support:

  * zero extension: done
  * sign extension: needed
  * arithmetic operators (add, sub, mul, div): needed

* Double floating point support

  This was started. "What's missing?" to be filled in.

* Intrinsics

  Lots of progress. "What's missing/incomplete?" to be filled in.

===-------------------------------------------------------------------------===