..
access-non-generic.ll
[NVPTX] Adds a new address space inference pass.
2016-03-20 20:59:20 +00:00
add-128bit.ll
addrspacecast-gvar.ll
addrspacecast.ll
aggr-param.ll
alias.ll
[CUDA] Die gracefully when trying to output an LLVM alias.
2016-01-23 21:12:20 +00:00
annotations.ll
arg-lowering.ll
arithmetic-fp-sm20.ll
arithmetic-int.ll
[NVPTX] expand mul_lohi to mul_lo and mul_hi
2016-01-22 19:47:26 +00:00
atomics.ll
bfe.ll
branch-fold.ll
Roll forward r242871
2015-07-29 18:59:09 +00:00
bug17709.ll
bug21465.ll
[NVPTX] run SROA after NVPTXFavorNonGenericAddrSpaces
2015-06-09 00:05:56 +00:00
bug22246.ll
bug22322.ll
bug26185-2.ll
[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection
2016-05-02 18:12:02 +00:00
bug26185.ll
[NVPTX] Handle ldg created from sign-/zero-extended load
2016-04-05 12:38:01 +00:00
bypass-div.ll
Use 32-bit divides instead of 64-bit divides where possible.
2015-08-11 22:16:34 +00:00
call-with-alloca-buffer.ll
Add NVPTXPeephole pass to reduce unnecessary address cast
2015-06-24 20:20:16 +00:00
callchain.ll
calling-conv.ll
combine-min-max.ll
[NVPTX] Let NVPTX backend detect integer min and max patterns.
2015-08-26 23:22:02 +00:00
compare-int.ll
constant-vectors.ll
convergent-mir-call.ll
[NVPTX] Use different, convergent MIs for convergent calls.
2016-03-01 19:24:03 +00:00
convert-fp.ll
convert-int-sm20.ll
ctlz.ll
ctpop.ll
cttz.ll
debug-file-loc.ll
[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
2016-04-15 15:57:41 +00:00
disable-opt.ll
[NVPTX] Disable performance optimizations when OptLevel==None
2016-02-04 04:15:36 +00:00
div-ri.ll
envreg.ll
extloadv.ll
[NVPTX] expand extload/truncstore for vectors of floats
2015-07-01 21:32:42 +00:00
fast-math.ll
fma-assoc.ll
SelectionDAG: Prefer to combine multiplication with less uses for fma
2015-08-11 19:21:46 +00:00
fma-disable.ll
fma.ll
fp16.ll
fp-contract.ll
fp-literals.ll
function-align.ll
generic-to-nvvm.ll
global-addrspace.ll
[NVPTX] Allow undef value as global initializer
2015-08-22 05:40:26 +00:00
global-ctor-empty.ll
[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
2016-01-30 01:07:38 +00:00
global-ctor.ll
[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
2016-01-30 01:07:38 +00:00
global-dtor.ll
[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
2016-01-30 01:07:38 +00:00
global-ordering.ll
global-visibility.ll
[NVPTX] Do not emit .hidden or .protected directives as they are not allowed by PTX.
2016-01-15 23:57:53 +00:00
globals_init.ll
The constant initialization for globals in NVPTX is generated as an
2015-06-09 16:29:34 +00:00
globals_lowering.ll
Force relocation mode to be default, regardless of what is passed to the backend.
2015-06-30 17:18:00 +00:00
gvar-init.ll
half.ll
i1-global.ll
i1-int-to-fp.ll
i1-param.ll
i8-param.ll
imad.ll
implicit-def.ll
inline-asm.ll
intrin-nocapture.ll
Reapply 239795 - [InstCombine] Propagate non-null facts to call parameters
2015-06-16 20:24:25 +00:00
intrinsic-old.ll
intrinsics.ll
[NVPTX] Added missing test case for llvm.nvvm.sqrt.f NVPTX intrinsic
2015-06-23 18:22:17 +00:00
isspacep.ll
ld-addrspace.ll
ld-generic.ll
ldparam-v4.ll
ldu-i8.ll
ldu-ldg.ll
ldu-reg-plus-offset.ll
lit.local.cfg
load-sext-i1.ll
load-with-non-coherent-cache.ll
[NVPTX] Use LDG for pointer induction variables.
2015-08-05 23:11:57 +00:00
local-stack-frame.ll
[NVPTX] Move NVPTXPeephole after NVPTXPrologEpilogPass
2015-07-01 20:08:06 +00:00
loop-vectorize.ll
[NVPTX] declare no vector registers
2015-07-10 04:31:56 +00:00
lower-aggr-copies.ll
Revert "Change memcpy/memset/memmove to have dest and source alignments."
2015-11-19 05:56:52 +00:00
lower-alloca.ll
Add NVPTXLowerAlloca pass to convert alloca'ed memory to local address
2015-06-17 22:31:02 +00:00
lower-kernel-ptr-arg.ll
[NVPTX] convert pointers in byval kernel arguments to global
2015-07-31 21:44:14 +00:00
machine-sink.ll
MachineSink-call.ll
[NVPTX] Annotate call machine instructions as calls.
2016-02-17 17:46:50 +00:00
MachineSink-convergent.ll
[NVPTX] Test that MachineSink won't sink across llvm.cuda.syncthreads.
2016-02-17 17:46:52 +00:00
managed.ll
misaligned-vector-ldst.ll
module-inline-asm.ll
mulwide.ll
noduplicate-syncthreads.ll
nounroll.ll
nvcl-param-align.ll
nvvm-reflect-module-flag.ll
[NVPTX] Read __CUDA_FTZ from module flags in NVVMReflect.
2016-04-01 01:09:07 +00:00
nvvm-reflect.ll
param-align.ll
pr13291-i1-store.ll
[NVPTX] roll forward r239082
2015-06-04 21:28:26 +00:00
pr16278.ll
pr17529.ll
refl1.ll
reg-copy.ll
[NVPTX] allow register copy between float and int
2015-08-01 18:02:12 +00:00
rotate.ll
rsqrt.ll
sched1.ll
sched2.ll
sext-in-reg.ll
sext-params.ll
shift-parts.ll
simple-call.ll
sm-version-20.ll
sm-version-21.ll
sm-version-30.ll
sm-version-32.ll
sm-version-35.ll
sm-version-37.ll
sm-version-50.ll
sm-version-52.ll
sm-version-53.ll
speculative-execution-divergent-target.ll
Move divergent-target test into CodeGen/NVPTX because it requires an NVPTX target.
2016-04-15 01:20:52 +00:00
st-addrspace.ll
st-generic.ll
surf-read-cuda.ll
[NVPTX] roll forward r239082
2015-06-04 21:28:26 +00:00
surf-read.ll
surf-write-cuda.ll
surf-write.ll
symbol-naming.ll
Have a single way for creating unique value names.
2015-11-22 00:16:24 +00:00
TailDuplication-convergent.ll
Don't tail-duplicate blocks that contain convergent instructions.
2016-02-22 17:50:52 +00:00
tex-read-cuda.ll
[NVPTX] roll forward r239082
2015-06-04 21:28:26 +00:00
tex-read.ll
texsurf-queries.ll
tuple-literal.ll
vec8.ll
vec-param-load.ll
vector-args.ll
vector-call.ll
Fix a bunch of trivial cases of 'CHECK[^:]*$' in the tests. NFCI
2015-08-10 19:01:27 +00:00
vector-compare.ll
vector-global.ll
vector-loads.ll
vector-return.ll
vector-select.ll
vector-stores.ll
weak-global.ll
weak-linkage.ll
