llvm/test/Transforms/LoopVectorize/AArch64
Silviu Baranga 39fbde60e1 [SCEV] Introduce a guarded backedge taken count and use it in LAA and LV
Summary:
When the backedge taken codition is computed from an icmp, SCEV can
deduce the backedge taken count only if one of the sides of the icmp
is an AddRecExpr. However, due to sign/zero extensions, we sometimes
end up with something that is not an AddRecExpr.

However, we can use SCEV predicates to produce a 'guarded' expression.
This change adds a method to SCEV to get this expression, and the
SCEV predicate associated with it.

In HowManyGreaterThans and HowManyLessThans we will now add a SCEV
predicate associated with the guarded backedge taken count when the
analyzed SCEV expression is not an AddRecExpr. Note that we only do
this as an alternative to returning a 'CouldNotCompute'.

We use new feature in Loop Access Analysis and LoopVectorize to analyze
and transform more loops.

Reviewers: anemet, mzolotukhin, hfinkel, sanjoy

Subscribers: flyingforyou, mcrosier, atrick, mssimpso, sanjoy, mzolotukhin, llvm-commits

Differential Revision: http://reviews.llvm.org/D17201

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265535 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 13:18:26 +00:00
..
aarch64-unroll.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
arbitrary-induction-step.ll [AArch64] Turn on by default interleaved access vectorization 2015-09-01 11:26:46 +00:00
arm64-unroll.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
backedge-overflow.ll [SCEV] Introduce a guarded backedge taken count and use it in LAA and LV 2016-04-06 13:18:26 +00:00
deterministic-type-shrinkage.ll [LoopVectorize] Use MapVector rather than DenseMap for MinBWs. 2015-11-26 20:39:51 +00:00
first-order-recurrence.ll [LoopUtils, LV] Fix PR26734 2016-03-03 16:12:01 +00:00
gather-cost.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
interleaved_cost.ll [AArch64] Turn on by default interleaved access vectorization 2015-09-01 11:26:46 +00:00
lit.local.cfg
loop-vectorization-factors.ll [VectorUtils] Don't try and truncate PHIs to a smaller bitwidth 2016-03-30 10:11:43 +00:00
reduction-small-size.ll [LV] Relax Small Size Reduction Type Requirement 2015-09-10 21:12:57 +00:00
sdiv-pow2.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
type-shrinkage-insertelt.ll [LV] Add support for insertelt/extractelt processing during type truncation 2016-02-15 15:38:17 +00:00