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3cb0b0edd9
Most of this stuff was supporting the old deferred spill code insertion mechanism. Modern spillers just edit machine code in place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144484 91177308-0d34-0410-b5e6-96231b3b80d8
286 lines
10 KiB
C++
286 lines
10 KiB
C++
//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the VirtRegMap class.
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//
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// It also contains implementations of the Spiller interface, which, given a
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// virtual register map and a machine function, eliminates all virtual
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// references by replacing them with physical register references - adding spill
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// code as necessary.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "virtregmap"
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#include "VirtRegMap.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include <algorithm>
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using namespace llvm;
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STATISTIC(NumSpillSlots, "Number of spill slots allocated");
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STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
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//===----------------------------------------------------------------------===//
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// VirtRegMap implementation
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//===----------------------------------------------------------------------===//
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char VirtRegMap::ID = 0;
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INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
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bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
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MRI = &mf.getRegInfo();
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TII = mf.getTarget().getInstrInfo();
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TRI = mf.getTarget().getRegisterInfo();
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MF = &mf;
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LowSpillSlot = HighSpillSlot = NO_STACK_SLOT;
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Virt2PhysMap.clear();
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Virt2StackSlotMap.clear();
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Virt2SplitMap.clear();
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SpillSlotToUsesMap.clear();
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SpillSlotToUsesMap.resize(8);
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allocatableRCRegs.clear();
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for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
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E = TRI->regclass_end(); I != E; ++I)
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allocatableRCRegs.insert(std::make_pair(*I,
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TRI->getAllocatableSet(mf, *I)));
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grow();
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return false;
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}
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void VirtRegMap::grow() {
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unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
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Virt2PhysMap.resize(NumRegs);
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Virt2StackSlotMap.resize(NumRegs);
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Virt2SplitMap.resize(NumRegs);
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}
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unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
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int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
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RC->getAlignment());
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if (LowSpillSlot == NO_STACK_SLOT)
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LowSpillSlot = SS;
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if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
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HighSpillSlot = SS;
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assert(SS >= LowSpillSlot && "Unexpected low spill slot");
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unsigned Idx = SS-LowSpillSlot;
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while (Idx >= SpillSlotToUsesMap.size())
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SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
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++NumSpillSlots;
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return SS;
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}
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unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
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std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
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unsigned physReg = Hint.second;
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if (TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
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physReg = getPhys(physReg);
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if (Hint.first == 0)
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return (TargetRegisterInfo::isPhysicalRegister(physReg))
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? physReg : 0;
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return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
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}
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int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
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return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
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}
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void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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assert((SS >= 0 ||
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(SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
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"illegal fixed frame index");
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Virt2StackSlotMap[virtReg] = SS;
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}
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void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
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if (!MF->getFrameInfo()->isFixedObjectIndex(FI)) {
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// If FI < LowSpillSlot, this stack reference was produced by
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// instruction selection and is not a spill
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if (FI >= LowSpillSlot) {
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assert(FI >= 0 && "Spill slot index should not be negative!");
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assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
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&& "Invalid spill slot");
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SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
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}
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}
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}
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void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isFI())
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continue;
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int FI = MO.getIndex();
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if (MF->getFrameInfo()->isFixedObjectIndex(FI))
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continue;
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// This stack reference was produced by instruction selection and
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// is not a spill
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if (FI < LowSpillSlot)
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continue;
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assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
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&& "Invalid spill slot");
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SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
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}
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}
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void VirtRegMap::rewrite(SlotIndexes *Indexes) {
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DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
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<< "********** Function: "
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<< MF->getFunction()->getName() << '\n');
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DEBUG(dump());
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SmallVector<unsigned, 8> SuperDeads;
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SmallVector<unsigned, 8> SuperDefs;
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SmallVector<unsigned, 8> SuperKills;
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for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
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MBBI != MBBE; ++MBBI) {
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DEBUG(MBBI->print(dbgs(), Indexes));
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for (MachineBasicBlock::iterator MII = MBBI->begin(), MIE = MBBI->end();
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MII != MIE;) {
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MachineInstr *MI = MII;
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++MII;
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for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
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MOE = MI->operands_end(); MOI != MOE; ++MOI) {
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MachineOperand &MO = *MOI;
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if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue;
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unsigned VirtReg = MO.getReg();
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unsigned PhysReg = getPhys(VirtReg);
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assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg");
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// Preserve semantics of sub-register operands.
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if (MO.getSubReg()) {
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// A virtual register kill refers to the whole register, so we may
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// have to add <imp-use,kill> operands for the super-register. A
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// partial redef always kills and redefines the super-register.
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if (MO.readsReg() && (MO.isDef() || MO.isKill()))
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SuperKills.push_back(PhysReg);
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if (MO.isDef()) {
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// The <def,undef> flag only makes sense for sub-register defs, and
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// we are substituting a full physreg. An <imp-use,kill> operand
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// from the SuperKills list will represent the partial read of the
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// super-register.
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MO.setIsUndef(false);
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// Also add implicit defs for the super-register.
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if (MO.isDead())
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SuperDeads.push_back(PhysReg);
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else
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SuperDefs.push_back(PhysReg);
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}
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// PhysReg operands cannot have subregister indexes.
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PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
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assert(PhysReg && "Invalid SubReg for physical register");
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MO.setSubReg(0);
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}
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// Rewrite. Note we could have used MachineOperand::substPhysReg(), but
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// we need the inlining here.
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MO.setReg(PhysReg);
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}
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// Add any missing super-register kills after rewriting the whole
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// instruction.
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while (!SuperKills.empty())
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MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
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while (!SuperDeads.empty())
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MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
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while (!SuperDefs.empty())
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MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
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DEBUG(dbgs() << "> " << *MI);
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// Finally, remove any identity copies.
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if (MI->isIdentityCopy()) {
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++NumIdCopies;
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if (MI->getNumOperands() == 2) {
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DEBUG(dbgs() << "Deleting identity copy.\n");
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RemoveMachineInstrFromMaps(MI);
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if (Indexes)
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Indexes->removeMachineInstrFromMaps(MI);
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// It's safe to erase MI because MII has already been incremented.
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MI->eraseFromParent();
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} else {
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// Transform identity copy to a KILL to deal with subregisters.
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MI->setDesc(TII->get(TargetOpcode::KILL));
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DEBUG(dbgs() << "Identity copy: " << *MI);
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}
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}
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}
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}
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// Tell MRI about physical registers in use.
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for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
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if (!MRI->reg_nodbg_empty(Reg))
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MRI->setPhysRegUsed(Reg);
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}
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void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
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const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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OS << "********** REGISTER MAP **********\n";
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for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
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OS << '[' << PrintReg(Reg, TRI) << " -> "
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<< PrintReg(Virt2PhysMap[Reg], TRI) << "] "
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<< MRI.getRegClass(Reg)->getName() << "\n";
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}
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}
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for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
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OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
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<< "] " << MRI.getRegClass(Reg)->getName() << "\n";
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}
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}
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OS << '\n';
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}
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void VirtRegMap::dump() const {
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print(dbgs());
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}
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