llvm/test/MC/PowerPC
Hal Finkel f8d179ba76 [PowerPC] Add support for the QPX vector instruction set
This adds support for the QPX vector instruction set, which is used by the
enhanced A2 cores on the IBM BG/Q supercomputers. QPX vectors are 256 bytes
wide, holding 4 double-precision floating-point values. Boolean values, modeled
here as <4 x i1> are actually also represented as floating-point values
(essentially  { -1, 1 } for { false, true }). QPX shares many features with
Altivec and VSX, but is distinct from both of them. One major difference is
that, instead of adding completely-separate vector registers, QPX vector
registers are extensions of the scalar floating-point registers (lane 0 is the
corresponding scalar floating-point value). The operations supported on QPX
vectors mirrors that supported on the scalar floating-point values (with some
additional ones for permutations and logical/comparison operations).

I've been maintaining this support out-of-tree, as part of the bgclang project,
for several years. This is not the entire bgclang patch set, but is most of the
subset that can be cleanly integrated into LLVM proper at this time. Adding
this to the LLVM backend is part of my efforts to rebase bgclang to the current
LLVM trunk, but is independently useful (especially for codes that use LLVM as
a JIT in library form).

The assembler/disassembler test coverage is complete. The CodeGen test coverage
is not, but I've included some tests, and more will be added as follow-up work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230413 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-25 01:06:45 +00:00
..
deprecated-p7.s
lcomm.s Object: BSS/virtual sections don't have contents 2014-09-26 22:32:16 +00:00
lit.local.cfg
ppc32-ba.s Allow large immediates for branch instructions in 32bit mode. 2014-08-08 20:57:58 +00:00
ppc64-abiversion.s [PowerPC] ELFv2 MC support for .abiversion directive 2014-07-20 22:56:57 +00:00
ppc64-encoding-4xx.s Use the full form of dccci and iccci from the early PPC 405 documents, 2014-08-09 13:58:31 +00:00
ppc64-encoding-6xx.s Add PPC 603's tlbld and tlbli instructions. 2014-08-04 23:49:45 +00:00
ppc64-encoding-bookII.s [PowerPC] Add support for dcbtst and icbt (prefetch) 2014-08-23 23:21:04 +00:00
ppc64-encoding-bookIII.s Refactor TLBIVAX and add tlbsx. 2014-07-30 22:51:15 +00:00
ppc64-encoding-e500.s Add features for PPC 4xx and e500/e500mc instructions. 2014-08-04 15:47:38 +00:00
ppc64-encoding-ext.s [PowerPC] Add asm support for cache-inhibited ld/st instructions 2014-11-30 10:15:56 +00:00
ppc64-encoding-fp.s [PowerPC] Add assembler support for mcrfs and friends 2015-01-15 01:00:53 +00:00
ppc64-encoding-spe.s Add support for SPE load/store from memory. 2014-08-08 16:43:49 +00:00
ppc64-encoding-vmx.s This change implements the following three logical vector operations: 2015-02-09 17:03:18 +00:00
ppc64-encoding.s [PowerPC] Support the (old) cntlz instruction alias 2015-02-10 18:45:02 +00:00
ppc64-errors.s
ppc64-fixup-apply.s @l and friends adjust their value depending the context used in. 2014-08-10 12:41:50 +00:00
ppc64-fixup-explicit.s
ppc64-fixups.s @l and friends adjust their value depending the context used in. 2014-08-10 12:41:50 +00:00
ppc64-initial-cfa.s Emit DWARF3 call frame information when DWARF3+ debug info is requested 2014-06-19 15:39:33 +00:00
ppc64-localentry-error1.s [PowerPC] ELFv2 MC support for .localentry directive 2014-07-20 23:06:03 +00:00
ppc64-localentry-error2.s [PowerPC] ELFv2 MC support for .localentry directive 2014-07-20 23:06:03 +00:00
ppc64-localentry.s [PowerPC] Fix PR 21652 - copy st_other bits on symbol assignment 2014-11-24 18:09:47 +00:00
ppc64-operands.s
ppc64-regs.s
ppc64-relocs-01.s
ppc64-tls-relocs-01.s
ppc-llong.s
ppc-machine.s
ppc-nop.s
ppc-reloc.s Add parsing of 'foo@local". 2014-12-17 06:23:35 +00:00
ppc-word.s
qpx.s [PowerPC] Add support for the QPX vector instruction set 2015-02-25 01:06:45 +00:00
tls-gd-obj.s
tls-ie-obj.s
tls-ld-obj.s
vsx.s This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions. 2015-02-18 16:21:46 +00:00