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llvm/test/CodeGen/NVPTX
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Artem Belevich 27140649cc [NVPTX] Added intrinsics for atom.gen.{sys|cta}.* instructions. 
These are only available on sm_60+ GPUs.

Differential Revision: https://reviews.llvm.org/D24943

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282607 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-28 17:25:38 +00:00
..
access-non-generic.ll
[NVPTX] Switch nvptx-use-infer-addrspace to true.
2016-08-19 20:46:45 +00:00
add-128bit.ll
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addrspacecast-gvar.ll
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addrspacecast.ll
[NVPTX] Switch nvptx-use-infer-addrspace to true.
2016-08-19 20:46:45 +00:00
aggr-param.ll
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aggregate-return.ll
[NVPTX] deal with all aggregate return types.
2016-07-20 18:39:52 +00:00
alias.ll
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annotations.ll
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arg-lowering.ll
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arithmetic-fp-sm20.ll
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arithmetic-int.ll
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atomics-with-scope.ll
[NVPTX] Added intrinsics for atom.gen.{sys|cta}.* instructions.
2016-09-28 17:25:38 +00:00
atomics.ll
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bfe.ll
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branch-fold.ll
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bug17709.ll
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bug21465.ll
[NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC.
2016-07-20 21:44:07 +00:00
bug22246.ll
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bug22322.ll
[NVPTX] Implement llvm.fabs.f32, llvm.max.f32, etc.
2016-09-09 21:07:26 +00:00
bug26185-2.ll
[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection
2016-05-02 18:12:02 +00:00
bug26185.ll
[NVPTX] Handle ldg created from sign-/zero-extended load
2016-04-05 12:38:01 +00:00
bypass-div.ll
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call-with-alloca-buffer.ll
Fix NVPTX/call-with-alloca-buffer.ll after r276777.
2016-07-26 18:28:33 +00:00
callchain.ll
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calling-conv.ll
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combine-min-max.ll
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compare-int.ll
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constant-vectors.ll
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convergent-mir-call.ll
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convert-fp.ll
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convert-int-sm20.ll
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ctlz.ll
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ctpop.ll
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cttz.ll
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debug-file-loc.ll
[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
2016-04-15 15:57:41 +00:00
disable-opt.ll
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div-ri.ll
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envreg.ll
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extloadv.ll
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fast-math.ll
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fma-assoc.ll
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fma-disable.ll
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fma.ll
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fp16.ll
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fp-contract.ll
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fp-literals.ll
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function-align.ll
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generic-to-nvvm-ir.ll
DebugInfo: New metadata representation for global variables.
2016-09-13 01:12:59 +00:00
generic-to-nvvm.ll
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global-addrspace.ll
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global-ctor-empty.ll
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global-ctor.ll
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global-dtor.ll
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global-ordering.ll
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global-visibility.ll
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globals_init.ll
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globals_lowering.ll
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gvar-init.ll
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half.ll
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i1-global.ll
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i1-int-to-fp.ll
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i1-param.ll
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i8-param.ll
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imad.ll
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implicit-def.ll
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inline-asm.ll
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intrin-nocapture.ll
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intrinsic-old.ll
NVPTX: Remove the legacy ptx intrinsics
2016-07-07 16:40:17 +00:00
intrinsics.ll
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isspacep.ll
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ld-addrspace.ll
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ld-generic.ll
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ldg-invariant.ll
[NVPTX] Use ldg for explicitly invariant loads.
2016-09-11 01:39:04 +00:00
ldparam-v4.ll
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ldu-i8.ll
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ldu-ldg.ll
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ldu-reg-plus-offset.ll
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lit.local.cfg
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load-sext-i1.ll
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load-with-non-coherent-cache.ll
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LoadStoreVectorizer.ll
[NVPTX] Enable the load-store vectorizer on nvptx.
2016-07-20 22:11:36 +00:00
local-stack-frame.ll
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loop-vectorize.ll
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lower-aggr-copies.ll
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lower-alloca.ll
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lower-kernel-ptr-arg.ll
[NVPTX] Improve lowering of byval args of device functions.
2016-07-20 18:39:47 +00:00
machine-sink.ll
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MachineSink-call.ll
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MachineSink-convergent.ll
NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0
2016-07-06 20:02:45 +00:00
managed.ll
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math-intrins.ll
[NVPTX] Implement llvm.fabs.f32, llvm.max.f32, etc.
2016-09-09 21:07:26 +00:00
misaligned-vector-ldst.ll
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module-inline-asm.ll
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mulwide.ll
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noduplicate-syncthreads.ll
NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0
2016-07-06 20:02:45 +00:00
nounroll.ll
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nvcl-param-align.ll
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nvvm-reflect-module-flag.ll
[NVPTX] Read __CUDA_FTZ from module flags in NVVMReflect.
2016-04-01 01:09:07 +00:00
nvvm-reflect.ll
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param-align.ll
[NVPTX] Make sure we adjust alignment at all call sites
2016-07-18 21:58:48 +00:00
pr13291-i1-store.ll
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pr16278.ll
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pr17529.ll
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refl1.ll
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reg-copy.ll
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reg-types.ll
[NVPTX] Use untyped (.b) integer registers in PTX.
2016-08-12 22:02:19 +00:00
rotate.ll
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rsqrt.ll
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sched1.ll
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sched2.ll
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sext-in-reg.ll
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sext-params.ll
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shfl.ll
[NVPTX] Add intrinsics for shfl instructions.
2016-06-09 20:04:08 +00:00
shift-parts.ll
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simple-call.ll
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sm-version-20.ll
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sm-version-21.ll
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sm-version-30.ll
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sm-version-32.ll
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sm-version-35.ll
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sm-version-37.ll
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sm-version-50.ll
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sm-version-52.ll
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sm-version-53.ll
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sm-version-60.ll
[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
2016-07-06 21:06:10 +00:00
sm-version-61.ll
[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
2016-07-06 21:06:10 +00:00
sm-version-62.ll
[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
2016-07-06 21:06:10 +00:00
speculative-execution-divergent-target.ll
Move divergent-target test into CodeGen/NVPTX because it requires an NVPTX target.
2016-04-15 01:20:52 +00:00
st-addrspace.ll
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st-generic.ll
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surf-read-cuda.ll
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surf-read.ll
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surf-write-cuda.ll
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surf-write.ll
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symbol-naming.ll
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TailDuplication-convergent.ll
NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0
2016-07-06 20:02:45 +00:00
tex-read-cuda.ll
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tex-read.ll
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texsurf-queries.ll
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tuple-literal.ll
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vec8.ll
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vec-param-load.ll
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vector-args.ll
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vector-call.ll
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vector-compare.ll
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vector-global.ll
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vector-loads.ll
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vector-select.ll
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vector-stores.ll
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weak-global.ll
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weak-linkage.ll
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zero-cs.ll
llvm/test/CodeGen/NVPTX/zero-cs.ll: Relax an expression to match in -Asserts.
2016-09-21 04:43:11 +00:00
zeroext-32bit.ll
Only emit extension for zeroext/signext arguments if type is < 32 bits
2016-06-27 20:22:22 +00:00