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llvm/test/CodeGen/Hexagon
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Krzysztof Parzyszek 733cec8f05 [Hexagon] Improve patterns with stack-based addressing 
- Treat bitwise OR with a frame index as an ADD wherever possible, fold it
  into addressing mode.
- Extend patterns for memops to allow memops with frame indexes as address
  operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275569 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 15:35:52 +00:00
..
intrinsics
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vect
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absaddr-store.ll
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absimm.ll
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adde.ll
[Hexagon] Enable the post-RA scheduler
2016-05-26 19:44:28 +00:00
addh-sext-trunc.ll
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addh-shifted.ll
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addh.ll
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addrmode-indoff.ll
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alu64.ll
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always-ext.ll
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args.ll
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ashift-left-right.ll
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Atomics.ll
[Hexagon] Handle expansion of cmpxchg
2016-06-22 16:07:10 +00:00
avoid-predspill-calleesaved.ll
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avoid-predspill.ll
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barrier-flag.ll
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base-offset-addr.ll
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base-offset-post.ll
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bit-eval.ll
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bit-extractu-half.ll
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bit-loop.ll
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bit-phi.ll
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bitconvert-vector.ll
[Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)
2016-06-27 15:08:22 +00:00
block-addr.ll
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block-ranges-nodef.ll
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branch-non-mbb.ll
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BranchPredict.ll
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brev_ld.ll
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brev_st.ll
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bugAsmHWloop.ll
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builtin-prefetch-offset.ll
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builtin-prefetch.ll
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calling-conv-2.ll
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callr-dep-edge.ll
[ScheduleDAG] Make sure to process all def operands before any use operands
2016-05-10 16:50:30 +00:00
cext-check.ll
[Hexagon] Simplify HexagonInstrInfo::isPredicable
2016-05-16 16:56:10 +00:00
cext-valid-packet1.ll
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cext-valid-packet2.ll
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cext.ll
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cexti16.ll
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cfi-late.ll
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cfi-offset.ll
[Hexagon] Use offsets relative to FP+8 in .cfi_offset instructions
2016-05-11 14:53:07 +00:00
checktabs.ll
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circ_ld.ll
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circ_ldd_bug.ll
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circ_ldw.ll
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circ_st.ll
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circ-load-isel.ll
[Hexagon] Remove dead nodes from SelectionDAG to avoid cycles
2016-05-13 18:48:15 +00:00
clr_set_toggle.ll
[Hexagon] Improve patterns with stack-based addressing
2016-07-15 15:35:52 +00:00
cmp_pred2.ll
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cmp_pred_reg.ll
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cmp_pred.ll
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cmp-extend.ll
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cmp-promote.ll
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cmp-to-genreg.ll
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cmp-to-predreg.ll
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cmp.ll
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cmpb_pred.ll
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cmpb-eq.ll
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combine_ir.ll
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combine.ll
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common-gep-basic.ll
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common-gep-icm.ll
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compound.ll
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const64.ll
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convertdptoint.ll
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convertdptoll.ll
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convertsptoint.ll
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convertsptoll.ll
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csr-func-usedef.ll
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ctlz-cttz-ctpop.ll
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ctor.ll
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dadd.ll
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dmul.ll
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double.ll
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doubleconvert-ieee-rnd-near.ll
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dsub.ll
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dualstore.ll
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duplex.ll
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early-if-conversion-bug1.ll
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early-if-phi-i1.ll
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early-if-spare.ll
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early-if.ll
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eh_return.ll
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eliminate-pred-spill.ll
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expand-condsets-basic.ll
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expand-condsets-pred-undef.ll
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expand-condsets-rm-segment.ll
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expand-condsets-undef.ll
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extload-combine.ll
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extract-basic.ll
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fadd.ll
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fcmp.ll
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float.ll
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floatconvert-ieee-rnd-near.ll
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fmul.ll
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frame.ll
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fsub.ll
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fusedandshift.ll
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gp-plus-offset-load.ll
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gp-plus-offset-store.ll
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gp-rel.ll
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hwloop1.ll
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hwloop2.ll
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hwloop3.ll
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hwloop4.ll
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hwloop5.ll
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hwloop-cleanup.ll
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hwloop-const.ll
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hwloop-crit-edge.ll
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hwloop-dbg.ll
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hwloop-le.ll
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hwloop-loop1.ll
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hwloop-lt1.ll
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hwloop-lt.ll
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hwloop-missed.ll
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hwloop-ne.ll
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hwloop-ph-deadcode.ll
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hwloop-pos-ivbump1.ll
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hwloop-preheader.ll
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hwloop-range.ll
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hwloop-recursion.ll
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hwloop-wrap2.ll
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hwloop-wrap.ll
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i1_VarArg.ll
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i8_VarArg.ll
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i16_VarArg.ll
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idxload-with-zero-offset.ll
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ifcvt-diamond-bad.ll
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ifcvt-edge-weight.ll
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indirect-br.ll
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inline-asm-qv.ll
[Hexagon] Recognize "q" and "v" in inline-asm as register constraints
2016-05-18 14:34:51 +00:00
insert4.ll
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insert-basic.ll
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lit.local.cfg
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loadi1-G0.ll
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loadi1-v4-G0.ll
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loadi1-v4.ll
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loadi1.ll
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macint.ll
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maxd.ll
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maxh.ll
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maxud.ll
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maxuw.ll
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maxw.ll
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mem-fi-add.ll
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memcpy-likely-aligned.ll
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memops1.ll
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memops2.ll
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memops3.ll
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memops-stack.ll
[Hexagon] Improve patterns with stack-based addressing
2016-07-15 15:35:52 +00:00
memops.ll
[Hexagon] Improve patterns with stack-based addressing
2016-07-15 15:35:52 +00:00
mind.ll
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minu-zext-8.ll
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minu-zext-16.ll
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minud.ll
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minuw.ll
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minw.ll
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misaligned-access.ll
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misched-top-rptracker-sync.ll
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mpy.ll
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mux-basic.ll
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newvaluejump2.ll
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newvaluejump.ll
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newvaluestore.ll
[Hexagon] Enable the post-RA scheduler
2016-05-26 19:44:28 +00:00
NVJumpCmp.ll
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opt-addr-mode.ll
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opt-fabs.ll
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opt-fneg.ll
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packetize_cond_inst.ll
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packetize-tailcall-arg.ll
[Hexagon] Packetize function call arguments with tail call instructions
2016-07-14 19:30:55 +00:00
peephole-op-swap.ll
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pic-jumptables.ll
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pic-local.ll
Start using shouldAssumeDSOLocal on Hexagon.
2016-06-22 19:09:14 +00:00
pic-regusage.ll
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pic-simple.ll
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pic-static.ll
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postinc-load.ll
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postinc-offset.ll
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postinc-store.ll
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pred-absolute-store.ll
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pred-gp.ll
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pred-instrs.ll
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predicate-copy.ll
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predicate-logical.ll
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predicate-rcmp.ll
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rdf-copy-undef2.ll
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rdf-copy.ll
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rdf-dead-loop.ll
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rdf-inline-asm-fixed.ll
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rdf-inline-asm.ll
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rdf-reset-kills.ll
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reg-scavengebug-3.ll
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reg-scavenger-valid-slot.ll
When looking for a spill slot in reg scavenger, find one that matches RC
2016-05-18 18:16:00 +00:00
relax.ll
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remove_lsr.ll
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remove-endloop.ll
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restore-single-reg.ll
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runtime-stkchk.ll
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sdata-array.ll
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sdata-basic.ll
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sdr-basic.ll
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sdr-shr32.ll
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section_7275.ll
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select-instr-align.ll
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shrink-frame-basic.ll
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signed_immediates.ll
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simple_addend.ll
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simpletailcall.ll
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split-const32-const64.ll
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stack-align1.ll
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stack-align2.ll
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stack-alloca1.ll
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stack-alloca2.ll
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static.ll
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store-shift.ll
[Hexagon] Add SDAG preprocessing step to expose shifted addressing modes
2016-06-22 20:08:27 +00:00
store-widen-aliased-load.ll
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store-widen-negv2.ll
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store-widen-negv.ll
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store-widen.ll
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storerinewabs.ll
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struct_args_large.ll
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struct_args.ll
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sube.ll
[Hexagon] Enable the post-RA scheduler
2016-05-26 19:44:28 +00:00
tail-call-mem-intrinsics.ll
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tail-call-trunc.ll
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tail-dup-subreg-abort.ll
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tail-dup-subreg-map.ll
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tfr-to-combine.ll
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tls_pic.ll
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tls_static.ll
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union-1.ll
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usr-ovf-dep.ll
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v60Intrins.ll
[Hexagon] Enable the post-RA scheduler
2016-05-26 19:44:28 +00:00
v60small.ll
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v60Vasr.ll
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vaddh.ll
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validate-offset.ll
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vec-pred-spill1.ll
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vector-align.ll
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vload-postinc-sel.ll
[Hexagon] Simplify (+fix) instruction selection for indexed loads/stores
2016-06-24 21:27:17 +00:00
vselect-pseudo.ll
[Hexagon] Expand VSelect pseudo instructions
2016-05-12 19:16:02 +00:00
vsplat-isel.ll
[Hexagon] Properly handle instruction selection of vsplat intrinsics
2016-05-12 17:21:40 +00:00
zextloadi1.ll
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