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99c9d5015c
On CPUs with the zero cycle zeroing feature enabled "movi v.2d" should be used to zero a vector register. This was previously done at instruction selection time, however the register coalescer sometimes widened multiple vregs to the Q width because of that leading to extra spills. This patch leaves the decision on how to zero a register to the AsmPrinter phase where it doesn't affect register allocation anymore. This patch also sets isAsCheapAsAMove=1 on FMOVS0, FMOVD0. This fixes http://llvm.org/PR27454, rdar://25866262 Differential Revision: http://reviews.llvm.org/D21826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274686 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
1.0 KiB
LLVM
36 lines
1.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s
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@varfloat = global float 0.0
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@vardouble = global double 0.0
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declare void @use_float(float)
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declare void @use_double(double)
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define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
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; CHECK-LABEL: test_csel:
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%tst1 = icmp ugt i32 %lhs32, %rhs32
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%val1 = select i1 %tst1, float 0.0, float 1.0
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store float %val1, float* @varfloat
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; CHECK-DAG: movi v[[FLT0:[0-9]+]].2d, #0
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; CHECK-DAG: fmov s[[FLT1:[0-9]+]], #1.0
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; CHECK: fcsel {{s[0-9]+}}, s[[FLT0]], s[[FLT1]], hi
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%rhs64 = sext i32 %rhs32 to i64
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%tst2 = icmp sle i64 %lhs64, %rhs64
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%val2 = select i1 %tst2, double 1.0, double 0.0
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store double %val2, double* @vardouble
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; FLT0 is reused from above on ARM64.
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; CHECK: fmov d[[FLT1:[0-9]+]], #1.0
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; CHECK: fcsel {{d[0-9]+}}, d[[FLT1]], d[[FLT0]], le
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call void @use_float(float 0.0)
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call void @use_float(float 1.0)
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call void @use_double(double 0.0)
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call void @use_double(double 1.0)
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ret void
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; CHECK: ret
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}
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