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74854f1432
This patch contains a pass that transforms CBZ/CBNZ/TBZ/TBNZ instructions into a conditional branch (Bcc), when the NZCV flags can be set for "free". This is preferred on targets that have more flexibility when scheduling Bcc instructions as compared to CBZ/CBNZ/TBZ/TBNZ (assuming all other variables are equal). This can reduce register pressure and is also the default behavior for GCC. A few examples: add w8, w0, w1 -> cmn w0, w1 ; CMN is an alias of ADDS. cbz w8, .LBB_2 -> b.eq .LBB0_2 ; single def/use of w8 removed. add w8, w0, w1 -> adds w8, w0, w1 ; w8 has multiple uses. cbz w8, .LBB1_2 -> b.eq .LBB1_2 sub w8, w0, w1 -> subs w8, w0, w1 ; w8 has multiple uses. tbz w8, #31, .LBB6_2 -> b.ge .LBB6_2 In looking at all current sub-target machine descriptions, this transformation appears to be either positive or neutral. Differential Revision: https://reviews.llvm.org/D34220. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306144 91177308-0d34-0410-b5e6-96231b3b80d8
29 lines
769 B
LLVM
29 lines
769 B
LLVM
; RUN: llc -o - %s -mattr=+arith-cbz-fusion | FileCheck %s
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; RUN: llc -o - %s -mcpu=cyclone | FileCheck %s
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target triple = "aarch64-unknown"
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declare void @foobar(i32 %v0, i32 %v1)
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; Make sure sub is scheduled in front of cbnz
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; CHECK-LABEL: test_sub_cbz:
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; CHECK: subs w[[SUBRES:[0-9]+]], w0, #13
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; CHECK: b.ne {{.?LBB[0-9_]+}}
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define void @test_sub_cbz(i32 %a0, i32 %a1) {
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entry:
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; except for the fusion opportunity the sub/add should be equal so the
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; scheduler would leave them in source order if it weren't for the scheduling
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%v0 = sub i32 %a0, 13
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%cond = icmp eq i32 %v0, 0
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%v1 = add i32 %a1, 7
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br i1 %cond, label %if, label %exit
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if:
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call void @foobar(i32 %v1, i32 %v0)
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br label %exit
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exit:
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call void @foobar(i32 %v0, i32 %v1)
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ret void
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}
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