llvm/test/CodeGen/AArch64/rotate.ll
Charlie Turner aca09a9d4b [ARM] Expand ROTL and ROTR of vector value types
Summary: After D13851 landed, we saw backend crashes when compiling the reduced test case included in this patch. The right fix seems to be to allow these vector types for expansion in instruction selection.

Reviewers: rengolin, t.p.northover

Subscribers: RKSimon, t.p.northover, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14082

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251401 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-27 10:25:20 +00:00

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LLVM

; RUN: llc < %s -mtriple=aarch64--linux-gnueabihf | FileCheck %s
;; This used to cause a backend crash about not being able to
;; select ROTL. Make sure if generates the basic ushr/shl.
define <2 x i64> @testcase(<2 x i64>* %in) {
; CHECK-LABEL: testcase
; CHECK: ushr {{v[0-9]+}}.2d
; CHECK: shl {{v[0-9]+}}.2d
%1 = load <2 x i64>, <2 x i64>* %in
%2 = lshr <2 x i64> %1, <i64 8, i64 8>
%3 = shl <2 x i64> %1, <i64 56, i64 56>
%4 = or <2 x i64> %2, %3
ret <2 x i64> %4
}