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261c94d576
Summary: * Similiar to the ARM backend yse the peephole optimizer to generate more conditional ALU operations; * Add predicated type with default always true to RR instructions in LanaiInstrInfo.td; * Move LanaiSetflagAluCombiner into optimizeCompare; * The ASM parser can currently only handle explicitly specified CC, so specify ".t" (true) where needed in the ASM test; * Remove unused MachineOperand flags; Reviewers: eliben Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D22072 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274807 91177308-0d34-0410-b5e6-96231b3b80d8 |
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AArch64 | ||
AMDGPU | ||
ARM | ||
BPF | ||
Generic | ||
Hexagon | ||
Inputs | ||
Lanai | ||
Mips | ||
MIR | ||
MSP430 | ||
NVPTX | ||
PowerPC | ||
SPARC | ||
SystemZ | ||
Thumb | ||
Thumb2 | ||
WebAssembly | ||
WinEH | ||
X86 | ||
XCore |