Krzysztof Parzyszek 8cb434aecf [Hexagon] Add aliases for vector loads/stores with no explicit offset ...

The mem(r0) instructions are treated as mem(r0+#0).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268661 91177308-0d34-0410-b5e6-96231b3b80d8

2016-05-05 18:38:35 +00:00

..

AArch64

MCParser: diagnose missing directional labels more clearly.

2016-04-11 19:50:46 +00:00

AMDGPU

AMDGPU/SI: Add support for AMD code object version 2.

2016-05-05 17:03:33 +00:00

ARM

Reapply: "ARM: put correct symbol index on indirect pointers in __thread_ptr.""

2016-04-26 18:29:16 +00:00

AsmParser

[LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC.

2016-04-19 23:51:52 +00:00

COFF

[MC] Create unique .pdata sections for every .text section

2016-05-02 23:22:18 +00:00

Disassembler

[mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions

2016-05-04 12:02:12 +00:00

ELF

[MC/ELF] Make the relaxation test more interesting.

2016-04-24 01:08:35 +00:00

Hexagon

[Hexagon] Add aliases for vector loads/stores with no explicit offset

2016-05-05 18:38:35 +00:00

Lanai

[lanai] isBrImm should accept any non-constant immediate.

2016-03-31 17:58:55 +00:00

MachO

CodeGen: Use PLT relocations for relative references to unnamed_addr functions.

2016-04-22 20:40:10 +00:00

Markup

…

Mips

Fix Mips Parser error reporting

2016-05-05 14:15:46 +00:00

PowerPC

This reverts commit r265505.

2016-04-28 20:00:42 +00:00

Sparc

Sparc: silently ignore .proc assembler directive

2016-03-28 14:00:11 +00:00

SystemZ

[SystemZ] Add SVC instruction

2016-04-11 14:35:39 +00:00

X86

[AVX512] VPACKUSWB/VPACKSSWB should not be encoded with EVEX.W=1. While there fix the execution domain for VPACKSSDW/VPACKUSDW.

2016-05-01 17:38:32 +00:00