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8669eef6f1
rewriteOperands() always performed liveness queries at the base index rather than the RegSlot/Base as apropriate for the machine operand. This could lead to illegal rewriting in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277661 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
2.0 KiB
YAML
71 lines
2.0 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass simple-register-coalescing,rename-independent-subregs -o - %s | FileCheck %s
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--- |
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define void @test0() { ret void }
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define void @test1() { ret void }
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...
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---
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# In the test below we have two independent def+use pairs of subregister1 which
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# can be moved to a new virtual register. The third def of sub1 however is used
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# in combination with sub0 and needs to stay with the original vreg.
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# CHECK-LABEL: name: test0
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# CHECK: S_NOP 0, implicit-def undef %0.sub0
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# CHECK: S_NOP 0, implicit-def undef %2.sub1
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# CHECK: S_NOP 0, implicit %2.sub1
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# CHECK: S_NOP 0, implicit-def undef %1.sub1
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# CHECK: S_NOP 0, implicit %1.sub1
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# CHECK: S_NOP 0, implicit-def %0.sub1
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# CHECK: S_NOP 0, implicit %0
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name: test0
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registers:
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- { id: 0, class: sreg_128 }
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body: |
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bb.0:
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S_NOP 0, implicit-def undef %0.sub0
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S_NOP 0, implicit-def %0.sub1
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S_NOP 0, implicit %0.sub1
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S_NOP 0, implicit-def %0.sub1
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S_NOP 0, implicit %0.sub1
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S_NOP 0, implicit-def %0.sub1
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S_NOP 0, implicit %0
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...
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---
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# Test for a bug where we would incorrectly query liveness at the instruction
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# index in rewriteOperands(). This should pass the verifier afterwards.
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# CHECK-LABEL: test1
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# CHECK: bb.0
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# CHECK: S_NOP 0, implicit-def undef %2.sub2
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# CHECK: bb.1
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# CHECK: S_NOP 0, implicit-def %2.sub1
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# CHECK-NEXT: S_NOP 0, implicit-def %2.sub3
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# CHECK-NEXT: S_NOP 0, implicit %2
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# CHECK-NEXT: S_NOP 0, implicit-def undef %0.sub0
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# CHECK-NEXT: S_NOP 0, implicit %2.sub1
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# CHECK-NEXT: S_NOP 0, implicit %0.sub0
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# CHECK: bb.2
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# CHECK: S_NOP 0, implicit %2.sub
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name: test1
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registers:
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- { id: 0, class: sreg_128 }
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- { id: 1, class: sreg_128 }
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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S_NOP 0, implicit-def undef %0.sub2
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S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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S_BRANCH %bb.2
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bb.1:
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S_NOP 0, implicit-def %0.sub1
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S_NOP 0, implicit-def %0.sub3
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%1 = COPY %0
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S_NOP 0, implicit %1
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S_NOP 0, implicit-def %1.sub0
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S_NOP 0, implicit %1.sub1
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S_NOP 0, implicit %1.sub0
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bb.2:
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S_NOP 0, implicit %0.sub2
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...
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