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289f83a7d4
Summary: Instead of instantiating the MipsFastISel class and checking if the target is supported in the overriden methods, we should perform that check before creating the class. This allows us to enable FastISel *only* for targets that truly support it, ie. MIPS32 to MIPS32R5. Reviewers: sdardis Subscribers: ehostunreach, llvm-commits Differential Revision: https://reviews.llvm.org/D24824 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284475 91177308-0d34-0410-b5e6-96231b3b80d8
15 lines
453 B
LLVM
15 lines
453 B
LLVM
; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \
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; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s
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; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently
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; supports AFGR64 only, which uses paired 32 bit registers.
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define zeroext i1 @f(double %value) {
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entry:
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; CHECK-LABEL: f:
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; CHECK: sdc1
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%value.addr = alloca double, align 8
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store double %value, double* %value.addr, align 8
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ret i1 false
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}
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