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efa6f4843e
Summary: [ls][bh] and [ls][bh]u cannot use sp-relative addresses and must therefore lower frameindex nodes such that there is a copy to a CPU16Regs register. This is now done consistently using a separate addressing mode that does not permit frameindex nodes. As part of this I've had to remove an optimization that reduced the number of instructions needed to work around the lack of sp-relative addresses on [ls][bh] and [ls][bh]u. This optimization used one of the eight CPU16Regs registers as a copy of the stack pointer and it's implementation was the root cause of many of the register vs register class mismatches. lw/sw can use sp-relative addresses but we ought to ensure that we use the correct version of lw/sw internally for things like IAS. This is not currently the case and this change does not fix this. However, this change does clean it up sufficiently well to fix the machine verifier failures. Also removed irrelevant functions from stchar.ll. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21062 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272882 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.7 KiB
LLVM
42 lines
1.7 KiB
LLVM
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@kkkk = global i32 67, align 4
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@llll = global i32 33, align 4
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@mmmm = global i32 44, align 4
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@nnnn = global i32 55, align 4
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@oooo = global i32 32, align 4
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@pppp = global i32 41, align 4
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@qqqq = global i32 59, align 4
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@rrrr = global i32 60, align 4
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@.str = private unnamed_addr constant [32 x i8] c"%i %i %i %i %i %i %i %i %i %i \0A\00", align 1
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define i32 @main() nounwind {
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entry:
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%0 = load i32, i32* @kkkk, align 4
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%1 = load i32, i32* @llll, align 4
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%add = add nsw i32 %0, 10
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%add1 = add nsw i32 %1, 10
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%2 = load i32, i32* @mmmm, align 4
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%sub = add nsw i32 %2, -3
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%3 = load i32, i32* @nnnn, align 4
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%add2 = add nsw i32 %3, 10
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%4 = load i32, i32* @oooo, align 4
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%add3 = add nsw i32 %4, 4
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%5 = load i32, i32* @pppp, align 4
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%sub4 = add nsw i32 %5, -5
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%6 = load i32, i32* @qqqq, align 4
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%sub5 = add nsw i32 %6, -10
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%7 = load i32, i32* @rrrr, align 4
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%add6 = add nsw i32 %7, 6
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%call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i32 0, i32 0), i32 %sub5, i32 %add6, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) nounwind
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%call7 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind
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ret i32 0
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}
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; 16: sw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Spill
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; 16: lw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Reload
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; 16: sw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Spill
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; 16: lw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Reload
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declare i32 @printf(i8* nocapture, ...) nounwind
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