Quentin Colombet 3a0fccf6a0 [AArch64] Fix bad register class constraint in fast-isel for TST instruction.
rdar://problem/20748715


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236273 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-30 22:27:20 +00:00
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