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https://github.com/RPCSX/llvm.git
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4a5c408c28
Summary: GCNSchedStrategy re-uses most of GenericScheduler, it's just uses a different method to compute the excess and critical register pressure limits. It's not enabled by default, to enable it you need to pass -misched=gcn to llc. Shader DB stats: 32464 shaders in 17874 tests Totals: SGPRS: 1542846 -> 1643125 (6.50 %) VGPRS: 1005595 -> 904653 (-10.04 %) Spilled SGPRs: 29929 -> 27745 (-7.30 %) Spilled VGPRs: 334 -> 352 (5.39 %) Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread Code Size: 36688188 -> 37034900 (0.95 %) bytes LDS: 1913 -> 1913 (0.00 %) blocks Max Waves: 254101 -> 265125 (4.34 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 1338220 -> 1438499 (7.49 %) VGPRS: 886221 -> 785279 (-11.39 %) Spilled SGPRs: 29869 -> 27685 (-7.31 %) Spilled VGPRs: 334 -> 352 (5.39 %) Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread Code Size: 34315716 -> 34662428 (1.01 %) bytes LDS: 1551 -> 1551 (0.00 %) blocks Max Waves: 188127 -> 199151 (5.86 %) Wait states: 0 -> 0 (0.00 %) Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrick Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: https://reviews.llvm.org/D23688 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279995 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
2.6 KiB
CMake
93 lines
2.6 KiB
CMake
set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
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tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
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tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
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tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
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add_public_tablegen_target(AMDGPUCommonTableGen)
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# List of all GlobalISel files.
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set(GLOBAL_ISEL_FILES
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AMDGPUCallLowering.cpp
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)
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# Add GlobalISel files to the dependencies if the user wants to build it.
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if(LLVM_BUILD_GLOBAL_ISEL)
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set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
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else()
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set(GLOBAL_ISEL_BUILD_FILES"")
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set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
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endif()
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add_llvm_target(AMDGPUCodeGen
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AMDILCFGStructurizer.cpp
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AMDGPUAlwaysInlinePass.cpp
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AMDGPUAnnotateKernelFeatures.cpp
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AMDGPUAnnotateUniformValues.cpp
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AMDGPUAsmPrinter.cpp
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AMDGPUCodeGenPrepare.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUTargetObjectFile.cpp
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AMDGPUIntrinsicInfo.cpp
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AMDGPUISelDAGToDAG.cpp
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AMDGPUMCInstLower.cpp
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AMDGPUMachineFunction.cpp
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AMDGPUOpenCLImageTypeLoweringPass.cpp
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AMDGPUSubtarget.cpp
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AMDGPUTargetMachine.cpp
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AMDGPUTargetTransformInfo.cpp
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AMDGPUISelLowering.cpp
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AMDGPUInstrInfo.cpp
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AMDGPUPromoteAlloca.cpp
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AMDGPURegisterInfo.cpp
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GCNHazardRecognizer.cpp
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GCNSchedStrategy.cpp
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600FrameLowering.cpp
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R600InstrInfo.cpp
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R600ISelLowering.cpp
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R600MachineFunctionInfo.cpp
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R600MachineScheduler.cpp
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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SIAnnotateControlFlow.cpp
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SIDebuggerInsertNops.cpp
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SIFixControlFlowLiveIntervals.cpp
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SIFixSGPRCopies.cpp
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SIFoldOperands.cpp
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SIFrameLowering.cpp
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SIInsertSkips.cpp
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SIInsertWaits.cpp
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SIInstrInfo.cpp
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SIISelLowering.cpp
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SILoadStoreOptimizer.cpp
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SILowerControlFlow.cpp
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SILowerI1Copies.cpp
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SIMachineFunctionInfo.cpp
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SIMachineScheduler.cpp
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SIRegisterInfo.cpp
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SIShrinkInstructions.cpp
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SITypeRewriter.cpp
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SIWholeQuadMode.cpp
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${GLOBAL_ISEL_BUILD_FILES}
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)
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add_subdirectory(AsmParser)
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add_subdirectory(InstPrinter)
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add_subdirectory(Disassembler)
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add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(Utils)
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